Intel S5520SC Dokumentacja Pobierz pdf (Strona 43)

Intel® Workstation Board S5520SC TPS Functional Architecture

Revision 1.7

Intel order number: E39530-010

 Bank Interleaving – Interleave cache-line data between participant ranks.

 Channel Interleaving – Interleave between the channel when not in Mirrored Channel

Mode.

 Socket Interleaving – Interleaved memory can spread between both CPU sockets when

NUMA mode is disabled, given both CPU sockets are populated and DDR3 DIMMs are

installed in slots for both sockets.

3.3.6 Memory Test

3.3.6.1 Integrated Memory BIST Engine

The Intel

Xeon

Processor 5500 series incorporate an integrated Memory Built-in Self Test

(BIST) engine that is enabled to provide extensive coverage of memory errors at both the

memory cells and the data paths emanating from the DDR3 DIMMs.

The BIOS also uses the Memory BIST to initialize memory at the end of the memory discovery

process.

3.3.7 Memory Scrub Engine

The Intel

Xeon

Processor 5500 Series incorporates a memory scrub engine, which performs

periodic checks on the memory cells, and identifies and corrects single-bit errors. Two types of

scrubbing operations are supported:

 Demand scrubbing – Executes when an error is encountered during normal read/write

of data.

 Patrol scrubbing – Proactively walks through populated memory space seeking soft

errors.

By default, the BIOS enables both demand scrubbing and patrol scrubbing.

Demand scrubbing is not possible when memory mirroring is enabled. Therefore, if the memory

is configured for mirroring, the BIOS disables it automatically.

3.3.8 Memory RAS

3.3.8.1 RAS Features

The Intel

Workstation Board S5520SC supports the following memory channel modes:

• Independent Channel Mode

• Mirrored Channel Mode – Provides Channel RAS feature

These channel modes are used in conjunction with the standard Memory Test (Built-in Self-Test

(BIST) and Memory Scrub engines to provide full RAS support.

Channel RAS feature is supported only if both CPU sockets are populated and support the right

population. For more information, refer to Section 3.3.9.

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Intel S5520SC Dokumentacja Strona 43