Intel CHIPSET 820E Instrukcja Użytkownika Strona 168
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Intel
®
820E Chipset
R
168 Design Guide
4.2. Component Placement and Interconnection Layout
Requirements
The layout requirements for each interconnection are explained in detail in the following sections:
• Crystal to CK133
• CK133 to DRCG
• MCH to DRCG
• DRCG to RDRAM channel
4.2.1. 14.318 MHz Crystal to CK133
The distance between the crystal and the CK133 should be minimized. The maximum trace length is
500 mils.
4.2.2. CK133 to DRCG
• Processor _div2
• VddIR – Used as a reference for 2.5 V signaling
Figure 88. CK133-to-DRCG Routing Diagram
Ground
Ground/Power Plane
6 mils
4.5 mils
1.4 mils
1.4 mils
6 mils
VddiR
6 mils
6 mils
Ground
6 mils
6 mils
CPU_div2
6 mils
6 mils
Ground
6 mils
ck133_drcg_route
VddIR and CPU_div2 must be routed as shown in Figure 88. Note that the VddIR pin can be connected
directly to 2.5 V near the DRCG if the 2.5 V plane extends near the DRCG. However, if a 2.5 V trace
must be used, it should originate at the CK133 and be routed as shown.
- 820E Chipset 1
- Contents 3
- Figures 8
- Revision History 12
- 1. Introduction 13
- 1.2. Reference Documents 14
- 1.3. System Overview 15
- 1.3.1. Chipset Components 16
- 1.3.2. Bandwidth Summary 17
- 1.3.3. System Configuration 18
- 1.4. Platform Initiatives 20
- 1.4.7. Expanded USB Support 21
- 1.4.8. Manageability 21
- 1.4.9. AC’97 23
- AC97_conn 24
- 2. Layout/Routing Guidelines 27
- (324-Ball 28
- 2.3. Intel 29
- Data Associated Strobe 33
- SBA[7:0] SB_STB 33
- 2.7.1. Stack-Up 34
- 2.7.2.1. RSL Routing 35
- 2.7.2.2. RSL Termination 38
- Required 40
- Length × Width = Area = C 41
- × Thickness of prepreg / [(ε 41
- ) (1.1)] 41
- Recommendation 47
- 2.7.2.7. Via Compensation 52
- 1,2,3,4,5,6,7,8,9,10 53
- RSL Signals High-Speed 57
- CMOS Signals 57
- CMOS Signal 57
- If Signal Routed from MCH 59
- 2.8. AGP 2.0 60
- Signal Groups 61
- Strobe in 2× 62
- Associated Strobes 62
- AGP_2x-4x_routing 63
- All AGP Interfaces 64
- 2.8.5. AGP Clock Routing 65
- 2.8.7. V 66
- Generation and TYPEDET# 66
- TYPEDET# (on Add-in Card) V 67
- (Supplied by MB) 67
- 2.8.8. V 68
- 1.5-V AGP Card 69
- 3.3-V AGP Card 69
- 2.8.9. Compensation 70
- 2.8.10. AGP Pull-Ups 70
- 1× 2× 4× 71
- (Preferred) 73
- “Right-Handed” Orientation 73
- (Alternate) 73
- 2.9. Hub Interface 74
- III Processor for the 77
- GND Plane 78
- 2.12. IDE Interface 79
- IDE_combo_cable_det 81
- IDE_dev_cable_det 82
- 2.13. AC’97 85
- CNR BoardMotherboard 87
- CNR Connector 87
- Valid Codec Configurations 90
- 2.13.3. AC’97 Routing 91
- 2.14. USB 92
- 2.15. ISA Support 93
- 2.17. SMBus/SMLink Interface 94
- Ω pull-up resistors to 3.3 V 95
- 2.18. PCI 96
- 2.19. RTC 96
- = (C2 × C3) / (C2 + C3) + C 97
- VCC3_3SBY 98
- 2.21. ICH2 PIRQ Routing 101
- 2.22. LAN Layout Guidelines 102
- Layout Section Previous 103
- Reference 103
- Design Guide Section 103
- 2.22.1.1. Bus Topologies 104
- Configuration A B C D 105
- 2.22.1.6. Impedances 106
- 2.22.1.7. Line Termination 106
- LAN_RXD0 LAN_CLK 106
- 2.22.2.1.2. Signal Isolation 108
- Top-Layer Routing 110
- Ground Plane 110
- Power Plane 110
- Bottom Layer Routing 110
- 82555 or Intel 111
- 2.22.3. Intel 112
- Distance Priority Guideline 114
- 2.22.4. Intel 115
- 82562ET / Intel 115
- MMBT3906 119
- 2.22.6. Intel 120
- 82562ET and Intel 120
- 82562EH Components’ Dual 120
- Footprint Guidelines 120
- Capacitors 122
- Capacitor Value 122
- Design Guide 123 123
- 2.24. ICH2 Design Checklist 125
- Ω ± 3 kΩ 129
- 2.25. ICH2 Layout Checklist 134
- Design Guide 135 135
- Table 46. LAN Connect I/F 135
- ≤ 0.25 inch max 137
- 138 Design Guide 138
- Term Definition 139
- Guideline Methodology 141
- 3.2.3. Pre-Layout Simulation 145
- 3.2.3.4. Simulation Criteria 146
- 3.2.4.3. Host Clock Routing 148
- 3.2.6. Validation 150
- Valid delay = T 151
- 3.3. Theory 152
- 3.3.3. Crosstalk Theory 153
- Decoupling 156
- Signal Layer A 157
- Signal Layer B 157
- 3.4.4. Clock Routing 160
- 3.5.1. V 161
- Guard Band 161
- 3.5.2. Ringback Levels 161
- 3.5.3. Overdrive Region 161
- 3.6. Conclusion 162
- 4. Clocking 163
- 820_clk_route 166
- NOTES: 167
- Requirements 168
- CPU_div2 168
- 4.2.3. MCH to DRCG 169
- 4.2.4. DRCG-to-RDRAM Channel 170
- 4.2.5. Trace Length 170
- Ground CLOCK/CLOCK# Ground 171
- PGA370 Designs 173
- 4.7. Unused Outputs 174
- Design Guide 175 175
- 5. System Manufacturing 177
- 5.1.2. Design Process 178
- 5.1.4. Recommended Stack-Up 179
- 5.1.5. Inner-Layer Routing 179
- #1 #2 #3 #4 #5 #6 180
- Not Routable 181
- 182 Design Guide 182
- 6.1. Power Delivery 183
- 5 V Dual Switch 185
- VCCVID 185
- VCC 2.5 185
- 2.5 VBSY 186
- 1.8 VSB 188
- Design Guide 191 191
- 6.2. ICH2 Power Plane Split 192
- 6.3. Thermal Design Power 193
- 6.4. Glue Chip 3 (Intel 193
- 820E Chipset Glue Chip) 193
- Appendix A: Reference Design 195
- Schematics (Uniprocessor) 195
- 196 Design Guide 196
- REVISION 0.5 197
- INTEL(R) 820E CHIPSET 197
- Block Diagram 198
- Device Table 198
- 370-PIN SOCKET 199
- Clock Synthesizer 201
- MMBT3904LT1 203
- Top Block Lock 206
- RIMM Sockets 207
- Super I/O 208
- AC’97 Audio 209
- EEPROMLAN 211
- CNR OR LAN DOWN 212
- Stuffing Option for 212
- LAN (82562EH) 213
- LAN (82562ET/EM) 214
- LAN (RJ11 For 82562EH) 215
- LAN (RJ45 For 82562ET/EM) 216
- STUFF FOR 82562EH ONLY 217
- STUFF FOR 82562EH 218
- STUFF FOR GILAD ONLY 218
- AGP Connector 220
- PCI Connectors 221
- IDE Connectors 223
- USB Connectors 224
- Parallel Port 225
- Serial Ports 226
- Keyboard/Mouse/Floppy 227
- Game Port 228
- Voltage Regulators 230
- Power Connector 232
- AGTL Termination 233
- PCI/AGP Pullups/Pulldowns 234
- Rambus* Termination 235
- Un-used Gates 236
- Hub Interface Connector 239
- For debug only 239
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