Intel CHIPSET 820E Instrukcja Użytkownika Strona 1

Intel® 820E Chipset Design Guide May 2001 Document Number: 298187-003R

Intel® 820E Chipset R 10 Design Guide Figure 100. 4.5 mil Stack-Up ...

Intel® 820E Chipset R 100 Design Guide 2.19.6. RTC Routing Guidelines • All RTC OSC signals (RTCX1, RTCX2, VBIAS) should be routed with trace

Intel® 820E Chipset R Design Guide 101 logic low. When the jumper is not populated, a low can still be read on the signal line if the effectiv

Intel® 820E Chipset R 102 Design Guide Interrupts B, D, E, and H service devices internal to the ICH2. Interrupts A, C, F, and G are unused and

Intel® 820E Chipset R Design Guide 103 Figure 64. ICH2 / LAN Connect Section ICH2_LAN_connect Dual footprint Intel® 82562EH/82562ET ICH2 Magn

Intel® 820E Chipset R 104 Design Guide 2.22.1.1. Bus Topologies The LAN Connect Interface can be configured in several topologies, as follows:

Intel® 820E Chipset R Design Guide 105 Figure 66. LOM/CNR Interconnect IO_subsys_LOM-CNR_intercommICH2Res.packCNR PLC cardBAPLCC D Table 23. L

Intel® 820E Chipset R 106 Design Guide Figure 67. LAN_CLK Routing Example LAN_RXD0 LAN_CLK 2.22.1.5. Crosstalk Consideration Crosstalk-induc

Intel® 820E Chipset R Design Guide 107 2.22.2. General LAN Routing Guidelines and Considerations 2.22.2.1. General Trace Routing Considerati

Intel® 820E Chipset R 108 Design Guide 2.22.2.1.1. Trace Geometry and Length The key factors in controlling trace EMI radiation are the trace

Intel® 820E Chipset R Design Guide 109 Figure 69. Ground Plane Separation Separate Chassis Ground Plane Good grounding requires the minim

Intel® 820E Chipset R Design Guide 11 Table 45. USB...

Intel® 820E Chipset R 110 Design Guide 2.22.2.3. 4-Layer Board Design Top-Layer Routing Sensitive analog signals are routed completely on the

Intel® 820E Chipset R Design Guide 111 should be kept at least 0.3 inch from the nearest receive trace. Possible exceptions are only where the

Intel® 820E Chipset R 112 Design Guide 2.22.3. Intel® 82562EH Home/PNA* Guidelines Table 24. Related Documents Title Doc # Intel® 82562EH HomeP

Intel® 820E Chipset R Design Guide 113 For noise-free and stable operation, place the crystal and associated discretes as close as possible to

Intel® 820E Chipset R 114 Design Guide 2.22.3.5. Critical Dimensions As shown in the following figure, there are three dimensions to consider d

Intel® 820E Chipset R Design Guide 115 2.22.3.5.3. Distance from LPF to Phone RJ11 Distance ‘C’ should be less than 1 inch. Regarding trace s

Intel® 820E Chipset R 116 Design Guide 2.22.4.2. Crystals and Oscillators To minimize the effects of EMI, clock sources should not be placed n

Intel® 820E Chipset R Design Guide 117 Figure 73. Critical Dimensions for Component Placement Intel® 82562ET / 82562EMB A ICH2 EEPROM Magneti

Intel® 820E Chipset R 118 Design Guide 2.22.4.4.2. Distance from the Intel® 82562ET Component to the Magnetics Module Distance ‘B’ in Figure 7

Intel® 820E Chipset R Design Guide 119 Figure 74. Termination Plane N/CRJ-45Magnetics ModuleRDPRDNTDPTDNTermination PlaneAdditional capacitanc

Intel® 820E Chipset R 12 Design Guide Revision History Rev. Description Date -001 • Initial Release June 2000 -002 • Minor edits for cl

Intel® 820E Chipset R 120 Design Guide There are four pins which are used to put the Intel 82562ET/EM controller in different operating states:

Intel® 820E Chipset R Design Guide 121 Figure 77. Dual-Footprint Analog Interface IO_subsys_dual_footprint_analog_IFMagneticsmodule TDPRJ45 I

Intel® 820E Chipset R 122 Design Guide • Traces from magnetics to connector must be shared and not stubbed. An RJ-11 connector that fits into t

Intel® 820E Chipset R Design Guide 123 Figure 78. Decoupling Capacitor Layout 3.3 V Core1.8 V Core1.8 V Standby3.3 V Standby3.3 V Core1.8 V St

Intel® 820E Chipset R 124 Design Guide 2.23. FWH Flash BIOS Guidelines The general compatibility guidelines and the design recommendations for

Intel® 820E Chipset R Design Guide 125 2.24. ICH2 Design Checklist This checklist highlights design considerations that should be reviewed be

Intel® 820E Chipset R 126 Design Guide Table 27. Hub Interface Checklist Items Recommendations Reason/Effect HL[11] No pull-up resistor is r

Intel® 820E Chipset R Design Guide 127 Table 31. Interrupt Interface Checklist Items Recommendations Reason/Effect PIRQ#[D:A] These signals

Intel® 820E Chipset R 128 Design Guide Table 32. GPIO Checklist Items Recommendations Reason/Effect GPIO pins GPIO[0:7]: • These pins are

Intel® 820E Chipset R Design Guide 129 Table 34. Power Management Checklist Items Recommendations Reason/Effect THRM# Connect to temperatur

Intel® 820E Chipset R Design Guide 13 1. Introduction The Intel® 820E Chipset Design Guide provides design recommendations for systems using

Intel® 820E Chipset R 130 Design Guide Table 36. System Management Checklist Items Recommendations Reason/Effect SMBDATA SMBCLK Requires exte

Intel® 820E Chipset R Design Guide 131 Table 39. Miscellaneous Signals Checklist Items Recommendations Reason/Effect SPKR No extra pull-up

Intel® 820E Chipset R 132 Design Guide Figure 73. 5VREF Circuitry Vcc supply (3.3 V) 5 V supplyTo system To systemVrefsys_des_5Vref_circ1 µF1 k

Intel® 820E Chipset R Design Guide 133 Checklist Items Recommendations Reason/Effect Cable Detect* • Host Side/Device Side Detection:  Conn

Intel® 820E Chipset R 134 Design Guide 2.25. ICH2 Layout Checklist Table 43. 8-Bit Hub Interface # Layout Recommendations Yes No Comments 1

Intel® 820E Chipset R Design Guide 135 Table 46. LAN Connect I/F # Layout Recommendations Yes No Comments 1 Stack-up: 5 mils wide, 10 mil spa

Intel® 820E Chipset R 136 Design Guide # Layout Recommendations Yes No Comments 20 Isolate I/O signals from high-speed signals. To minimi

Intel® 820E Chipset R Design Guide 137 Table 49. CK-SKS Clocking # Layout Recommendations Yes No Comments 1 CLK_33 goes to ICH2, FWH FLASH BI

Intel® 820E Chipset R 138 Design Guide This page is intentionally left blank.

Intel® 820E Chipset R Design Guide 139 3. Advanced System Bus Design Section 2.10 describes the recommendations for designing Intel 820E chip

Intel® 820E Chipset R 14 Design Guide 1.2. Reference Documents • Intel® 820 Chipset Family: 82820 Memory Controller Hub (MCH) Datasheet (docum

Intel® 820E Chipset R 140 Design Guide Term Definition Flight time Flight time is a timing equation term that includes the signal propagation

Intel® 820E Chipset R Design Guide 141 Term Definition Simultaneous switching output (SSO) effects Difference in electrical timing parameters

Intel® 820E Chipset R 142 Design Guide 3.2.1. Initial Timing Analysis Perform an initial timing analysis of the system using the following two

Intel® 820E Chipset R Design Guide 143 A designer using components other than those listed previously must evaluate additional combinations of

Intel® 820E Chipset R 144 Design Guide The following two tables were derived assuming the following: • CLKSKEW = 0.2 ns Note: This assumes tha

Intel® 820E Chipset R Design Guide 145 Table 53. Example TFLT_MIN Calculations1 (Frequency Independent) Driver Receiver THOLD ClkSKEW TCO_MIN

Intel® 820E Chipset R 146 Design Guide 3.2.3.3. Monte Carlo Analysis Perform a Monte Carlo Analysis to refine the passing solution space regio

Intel® 820E Chipset R Design Guide 147 The transmission line package models must be inserted between the output of the buffer and the net it i

Intel® 820E Chipset R 148 Design Guide AGTL+. Intragroup AGTL+ crosstalk involves interference between AGTL+ signals within the same group. (Se

Intel® 820E Chipset R Design Guide 149 Figure 74. PICD[1,0] Uniprocessor Topology ICH2Intel®PGA370 Z 0 = 60 Ω ± 15% 1.5 150 Ωpicd_unipro

Intel® 820E Chipset R Design Guide 15 1.3. System Overview The Intel 820E chipset is designed for Intel® Pentium® III microprocessors and is t

Intel® 820E Chipset R 150 Design Guide 3.2.5.2. Crosstalk Analysis AGTL+ crosstalk simulations can consider as non-coupled the processor core p

Intel® 820E Chipset R Design Guide 151 Figure 76. Test Load vs. Actual System Load VTTQQSETCLRDVccCLKRTESTTest loadDriver pinDriver padTREFTCO

Intel® 820E Chipset R 152 Design Guide 3.3. Theory 3.3.1. AGTL+ AGTL+ is the electrical bus technology used for the processor bus. This is an

Intel® 820E Chipset R Design Guide 153 3.3.3. Crosstalk Theory AGTL+ signals swing across a smaller voltage range and have a correspondingly s

Intel® 820E Chipset R 154 Design Guide Additional aggressors are possible in the z-direction, if adjacent signal layers are not routed in mutua

Intel® 820E Chipset R Design Guide 155 3.4. More Details and Insight 3.4.1. Textbook Timing Equations The “textbook” equations used to calcu

Intel® 820E Chipset R 156 Design Guide 3.4.2. Effective Impedance and Tolerance/Variation The impedance of the PCB must be controlled when the

Intel® 820E Chipset R Design Guide 157 3.4.3.2. Reference Planes and PCB Stack-Up It is strongly recommended that baseboard stack-up be arran

Intel® 820E Chipset R 158 Design Guide Figure 81. Layer Switch with Multiple Reference Planes (Same Type) lay_sw_mult_refplaneSignal Layer ASig

Intel® 820E Chipset R Design Guide 159 Figure 83. One Layer with Multiple Reference Planes 1lay_Mult_refplaneGroundSignal Layer APower 3.4.3.3

Intel® 820E Chipset R 16 Design Guide 1.3.1. Chipset Components The Intel 820E chipset consists of the Intel® 82820 Memory Controller Hub (MCH)

Intel® 820E Chipset R 160 Design Guide 3.4.4. Clock Routing Analog simulations are required to ensure that the clock net signal quality and ske

Intel® 820E Chipset R Design Guide 161 3.5.1. VREF Guard Band To account for noise sources that may affect the way an AGTL+ signal becomes val

Intel® 820E Chipset R 162 Design Guide 3.5.4. Flight Time Definition and Measurement Timing measurements consist of minimum and maximum flight

Intel® 820E Chipset R Design Guide 163 4. Clocking 4.1. Clock Generation Two clock generator components are required in an Intel 820E chipset-

Intel® 820E Chipset R 164 Design Guide The MCH uses the same clock for hub interface and AGP. It is important that the hub interface/AGP clocks

Intel® 820E Chipset R Design Guide 165 Table 56. Intel® 820E Chipset Platform Clock Skews Clock Symbols (see Figure 86) Relationship Skew Not

Intel® 820E Chipset R 166 Design Guide The following figure shows the Intel 820E chipset clock length routing guidelines. Figure 87. Intel® 820

Intel® 820E Chipset R Design Guide 167 Table 57. Intel® 820E Chipset Platform System Clock Cross-Reference CK133/DRCG Pin Name Component Pin

Intel® 820E Chipset R 168 Design Guide 4.2. Component Placement and Interconnection Layout Requirements The layout requirements for each inte

Intel® 820E Chipset R Design Guide 169 4.2.3. MCH to DRCG • PclkM • PclkN • VddIPD Figure 89. MCH-to-DRCG Routing Diagram GroundGround/Pow

Intel® 820E Chipset R Design Guide 17 FWH Flash BIOS The FWH Flash BIOS component is a key element in providing a new security and manageabili

Intel® 820E Chipset R 170 Design Guide 4.2.4. DRCG-to-RDRAM Channel The Direct RDRAM clock signals (CTM/CTM# and CFM/CFM#) are high-speed, impe

Intel® 820E Chipset R Design Guide 171 For line section D (DRCG to last RIMM), the CTM/CTM# must be length-matched within ±2 mils. (Exact matc

Intel® 820E Chipset R 172 Design Guide 4.3. DRCG Impedance Matching Circuit The external DRCG impedance matching circuit is shown in the follo

Intel® 820E Chipset R Design Guide 173 4.3.1. DRCG Layout Example Figure 95. DRCG Layout Example Rs - 39Ω(Keep trace from DRCG to R

Intel® 820E Chipset R 174 Design Guide 4.7. Unused Outputs All unused clock outputs must be tied to ground through a series resistor that has a

Intel® 820E Chipset R Design Guide 175 4.9. DRCG Frequency Selection and the DRCG+ 4.9.1. DRCG Frequency Selection Table and Jitter Specific

Intel® 820E Chipset R 176 Design Guide 4.9.2. DRCG+ Frequency Selection Schematic The DRCG+ frequency can be selected using two GPIOs connecte

Intel® 820E Chipset R Design Guide 177 5. System Manufacturing 5.1. Stack-Up Requirement The Intel 820E chipset platform requires a board stac

Intel® 820E Chipset R 178 Design Guide 5.1.2. Design Process To meet the tight tolerances required, a good design process is as follows: • Spe

Intel® 820E Chipset R Design Guide 179 5.1.4. Recommended Stack-Up Though numerous stack-up variations are possible, the following starting po

Intel® 820E Chipset R 18 Design Guide 1.3.3. System Configuration The following figures show typical platform configurations using the Intel 82

Intel® 820E Chipset R 180 Design Guide Figure 98. Microstrip (a) and Stripline (b) Cross Section for 28 ΩΩΩΩ Trace GG4.5 mils2.1 mils6 mils18 m

Intel® 820E Chipset R Design Guide 181 5.1.7. Testing Board Impedance The Intel Printed Circuit Board (PCB) Test Methodology document (order#

Intel® 820E Chipset R 182 Design Guide This page intentionally left blank.

Intel® 820E Chipset R Design Guide 183 6. System Design Considerations 6.1. Power Delivery 6.1.1. Terminology and Definitions Term Definitio

Intel® 820E Chipset R 184 Design Guide 6.1.2. Power Delivery of Intel® 820E Chipset Customer Reference Board Figure 101 shows the power delive

Intel® 820E Chipset R Design Guide 185 This design guide provides only examples. Many power distribution methods achieve similar results. When

Intel® 820E Chipset R 186 Design Guide 2.5 VBSY The 2.5 VSBY power plane is used to power the RDRAM core and the VCMOS rail on the RDRAMs. The

Intel® 820E Chipset R Design Guide 187 Figure 102. 1.8 V and 2.5 V Power Sequencing (Schottky Diode) 1.8 V2.5 Vdiode_1.8V&2.5V VDDQ The VD

Intel® 820E Chipset R 188 Design Guide 1.8 VSB The 1.8 VSB plane powers the logic to the resume well of the ICH2. This should not be used for V

Intel® 820E Chipset R Design Guide 189 Figure 103. Example 1.8V/3.3V Power Sequencing Circuit Q1 PNP

Intel® 820E Chipset R Design Guide 19 Figure 3. Intel® 820E Chipset Platform Dual-Processor Performance Desktop Block Diagram I/O Controller

Intel® 820E Chipset R 190 Design Guide Figure 104. Example 3.3V/5V REF Sequencing Circuitry VCC Supply(3.3 V)5 V Supply1 K1 µFTo System VREF To

Intel® 820E Chipset R Design Guide 191 Figure 105. Use a GPO to Reduce DRCG Frequency DRCGGPOS0S0gpo_drcg-freq 6.1.5.2. Option 2: Increase th

Intel® 820E Chipset R 192 Design Guide 6.2. ICH2 Power Plane Split The following example shows the power plane splits for the ICH2. Figure 106

Intel® 820E Chipset R Design Guide 193 6.3. Thermal Design Power The thermal design power is the estimated maximum possible expected power ge

Intel® 820E Chipset R 194 Design Guide More information regarding this component is available from the vendors listed in the following table. T

Intel® 820E Chipset R Design Guide 195 Appendix A: Reference Design Schematics (Uniprocessor) This chapter provides the schematic diagrams f

Intel® 820E Chipset R 196 Design Guide This page is intentionally left blank.

5-23-2000_9:18 1REVISION 0.5FCPGA 2 RIMM ICH2 REFERENCE SCHEMATICSDRAWN BY:LAST REVISED: SHEET:FOLSOM, CALIFORNIA 956301900 PRAIRIE CITY ROAD87 6 54 3

25-23-2000_9:18BLOCK DIAGRAMDRAWN BY:LAST REVISED: SHEET:FOLSOM, CALIFORNIA 956301900 PRAIRIE CITY ROAD87 6 54 32 1ABCD12345678DCBAPCG PLATFORM DESIGN

3-20-2000_10:15 3PROCESSOR CONNECTORVID0VID1VID2VID333VID[3:0]0.1UFC80JP16123RS#0RS#1RS#26RS#[2:0]HREQ#0HREQ#1HREQ#2HREQ#3HREQ#46HREQ#[4:0]HA#3HA#4HA#

Intel® 820E Chipset R 2 Design Guide Information in this document is provided in connection with Intel® products. No license, express or imp

Intel® 820E Chipset R 20 Design Guide 1.4. Platform Initiatives 1.4.1. Direct Rambus RAM (RDRAM*) The Direct Rambus RAM (RDRAM) initiative pro

3-20-2000_10:15PROCESSOR CONNECTOR40.1UFC4330.1UFC4320.1UFC4340.1UFC4350.1UFC431TDOR51122C42810PFR5141KR51547R5161504.7UFC436210.1UFC429C43720%33UF214

3-20-2000_14:02CLOCK SYNTHESIZER5JP2010KR230C36482PF4,7SEL133/100#4PFC363CK133_XINSIO_14MHZ_RIHC_14MHZ_RIHC_48MHZ_RTEST_CLK66_RICH_CLK66_RMCH_CLK66_RS

3-20-2000_14:02MCH6RAMREF6,11RAMREF_R0.1UFC1830.1UFC158HD#[63:0]3,37HD#0HD#1HD#2HD#3HD#4HD#5HD#6HD#7HD#8HD#9HD#10HD#11HD#12HD#13HD#14HD#15HD#16HD#17HD

3-20-2000_14:02MCH74.7KR248PWROK8,9,34,36U1414713 12HL107,8GAD1GAD2GAD3GAD4GAD5GAD6GAD7GAD8GAD9GAD10GAD11GAD12GAD13GAD14GAD15GAD16GAD17GAD18GAD19GAD20

3-20-2000_14:02 8ICH2ICH_HLCOMPGPIO18VDDQVCC3_3VCC1_8SBYVCC2_5SBYVCC2_54,6,37CPURST#9,36RSMRST#9,35SLP_S5#6,8,10,11,12,24,25,26,27PCIRST#4,8,36PWRGOOD

3-20-2000_10:15 9ICH2U13U20B15D13D12F19U21F20B16D16E22V21W16AA13V19V20G21D17G19E21C15R20AB13W12AB11U19K4K3K2Y20W19W13AB12Y13W22M4Y11R21W15Y17C22D21D22

3-20-2000_10:15FWH108.2KR303FGPI0FGPI1R30710KR30410KTBLK_LCK9,12LFRAME#/FWH49,12LAD3/FWH3LAD2/FWH29,12LAD1/FWH19,12LAD0/FWH09,126,8,11,12,24,25,26,27P

3-20-2000_10:29RIMM SOCKETS11C610.1UFR2028-1%R2628-1%6,11RAMREF4,9,11,15,38SMBDATA_CORERCMD_ARSCK_ARDQA0_ARDQA1_ARDQA2_ARDQA3_ARDQA4_ARDQA5_ARDQA6_ARD

3-20-2000_10:15 12SUPER I/OR3134.7KKBCLK319LPC_PME#U17271845441511109365539685148396777309584988792901617787574737271706968293585926242523222120565763

3-20-2000_10:15 13AUDIO13,14VCC5_AUDIOAC_BITCLK9,150.1UFC3589,16AC_SDATAOUTAC_SDATAIN016AC_SYNC16R560KR1060KR770KRX3D_CU232282717161058331113124443403

Intel® 820E Chipset R Design Guide 21 1.4.5. Integrated LAN Controller The ICH2 component incorporates an integrated LAN Controller. Its bus

3-20-2000_10:15 14AUDIOLNLVL_L_R13LNLVL_OUT_LR220KR420K U18765123413MIC_IN4.7KR304.7KR514.7KR274.7KR5213CD_R13CD_L13CD_REFR184.7KR254.7KLINE_IN_R13LIN

3-20-2000_14:56 15COMMUNICATION AND NETWORK RISER (CNR)J2A10A19B9B27A18B23B16A26B2B1A2A1B17B13B10B7A17A14A9A6A3B19B15B18A16A15A13A22B21A21B22A25B25B12

163-20-2000_10:298LAN_RXD0_ICH2LAN_TXD2_ICH28RP53225%1234567815LAN_RXD2_CNR15LAN_RXD1_CNR15LAN_RXD0_CNR15LAN_TXD2_CNR15LAN_TXD1_CNR15AC_SYNC_CNR9AC_SD

3-20-2000_10:29 17LAN (82562EH)18,19,20LAN_SPEEDLEDR28710K18,21LAN_CLK_X118,21LAN_CLK_X21KR286R3411K1KR364R36510K10KR3465%R36710K16,18LAN_RESET16,18LA

183-20-2000_10:29R2541201%19,20,21LAN_RDM19,20,21LAN_RDP16,17LAN_RESET16LAN_RXD216,17LAN_CLK16,17LAN_RXD016LAN_RXD119,20LAN_ACTLED17,19,20LAN_LILED19,

3-20-2000_14:53 19LAN (RJ11)U28101116151476512398413122KV20%C3331500PF5%10MR3750KR3744.7UHL2518,20LAN_TDP18,20LAN_TDM18,20,21LAN_RDP18,20,21LAN_RDMR33

3-20-2000_16:55 20LAN (RJ45)CR1112U2710111615147651239841312J16141312108642119753115 16C3180.1UF0.1UFC329R113330R33433018,19LAN_ACTLED17,18,19LAN_SPEE

3-20-2000_11:31 21LANR37851.11%25MHZY51220MHZY2219,15EE_DOUT_ICH29,15EE_SHCLK_ICH215EE_CS_ICH2_OB1%51.1R37610%0.022UFC365R377R380U228342156717,18LAN_C

22LAN25V20%0.1UFC387C3880.1UF20%25V25V20%0.1UFC389C3900.1UF20%25V25V20%0.1UFC384C3850.1UF20%25V25V20%0.1UFC380 C3810.1UF20%25V 25V20%0.1UFC382 C3830.1

3-20-2000_11:31SYSTEM232.2KR103JP1GPIO23_FPLEDU1414756U1443714R253330IRRX121MR252SP112IDEACTS#2727IDEACTP#R34510KR34410KJP24123JP23321R3264.7KJP223214

Intel® 820E Chipset R 22 Design Guide Function Disable The ICH2 provides the ability to disable the following functions: AC’97 Modem, AC’97 Aud

3-20-2000_10:15AGP CONNECTOR2424,34TYPEDET#R208200-1%7 GAD[31:0]GAD0GAD2GAD4GAD6GAD9GAD11GAD13GAD15GAD16GAD18GAD20GAD22GAD24GAD26GAD28GAD30GAD1GAD3GAD

PCI CONNECTORS 1 AND 23-20-2000_10:15 2525,26PTCK8,24,25,26,38 PIRQ#B8,25,26,38 PIRQ#D5PCLK18,38PREQ#0C_BE#1C_BE#0C_BE#2C_BE#3C_BE#0C_BE#3C_BE#2C_BE#1

PCI CONNECTORS 3 AND 43-20-2000_10:15 26VAUX_JPR110R107SDONEP326SDONEP426SBOP326SBOP426PRSNT#3126PRSNT#3226PRSNT#4126PRSNT#4226PU3_ACK64#26PU3_REQ64#2

3-20-2000_10:15IDE CONNECTORS2727PCIRST_BUF#6,8,10,11,12,24,25,26PCIRST#9SDCS#18,38IRQ159PIORDY8,38IRQ149PDCS#19PDIOW#9SDIOW#9SDIOR#33R3334.7KR336470R

3-20-2000_10:15USB CONNECTORS28R5020KUSBV0USBG0USBV1USBD1NUSBD1PUSBG110KR979OC#0R83330KR480KR500KUSBP1N_RUSBP1P_R4.7KR9124USBAGP+R410KR420K9USBP0N9USB

3-20-2000_10:15PARALLEL PORT29PDR7_RPDR6_RPDR5_RPDR4_RPDR3_RSLIN#_RPDR2_RPAR_INIT#_RVCC5_DB25_CRSLCT12PE12BUSY12ACK#12SLIN#12J6P15P16P13P23P10P25P12P2

3-20-2000_10:15SERIAL PORTS30CTS1_CDTR1_CDCD1_CRTS0_CDTR0_CRXD0_CDSR0_CTXD1_CRXD1_CRTS1_CU61918171514131211123456789101620TXD11212DCD#112RTS#112RXD112

3-20-2000_10:15 31KEYBOARD/MOUSE/FLOPPYRDATA#12TRK#012DSKCHG#12HDSEL#12WGATE#12WDATA#12STEP#12DIR#12DS#012MTR#01212INDEX#DRVDEN#112DRVDEN#012L1312L142

GAME PORT324.7KR354.7KR3947R381KR331KR32R361KR371K12MIDI_IN12J1BUTTON212J2BUTTON2 5%R242.2K5%2.2KR2347R345%2.2KR225%2.2KR2112 JOY2Y12JOY1Y12 MIDI_OUT1

3-20-2000_10:15 33VRM 8.4IFB_QQ2156783214VID3VID0VID2VID1VID[3:0]3C4722200UF12C4711200UF12C4691200UF12C4681200UF12R715.1-5%OUTENVRM_PWRGD4,8,9,362200U

Intel® 820E Chipset R Design Guide 23 1.4.9. AC’97 The Audio Codec ’97 (AC’97) specification defines a digital interface that can be used to a

3-20-2000_10:15 34VOLTAGE REGULATORS100-1%R538100-1%R539100-1%R133100-1%R134301-1%R311131-1%R3095.1-5%R135R1461.21K-1%1%R1413017,8,9,36PWROKR3311K8,9,

3-20-2000_10:15 35VOLTAGE REGULATORSQ1956783214301-1%R509CMDSH-3CR9CAR29510KSBY_ITH_R100UFC31421C3120.1UFV_BOOSTC3064.7UF12C2991000PFC292100PF100PFC29

3-20-2000_10:15POWER CONNECTOR3610KR536VCOREDETU3147111213RSTBTN_SWU207143 4 7,8,9,34PWROK0KR3394.7KR349R3420K1MR288R25122KR3474.7KR34322U187148109PWR

3-20-2000_10:15 373,6HREQ#062RP298765432162RP308765432162RP338765432162RP348765432162RP218765432162RP228765432162RP238765432162RP248765432162RP2587654

3-20-2000_10:15PCI/AGP PULLUPS/PULLDOWNS38ST07,24ST17,247,24ST2R5078.2KSBSTB#7,247,24SBSTB7,24GGNT#WBF#7,247,24PIPE#PIRQ#B8,24,25,26PIRQ#A8,24,25,268.

3-20-2000_10:15 39RAMBUS TERMINATION11TERM_ROW[2:0]TERM_ROW1TERM_ROW0TERM_ROW211TERM_DQB[8:0]TERM_DQB0TERM_DQB2TERM_DQB3TERM_DQB4TERM_DQB5TERM_DQB6TER

3-20-2000_10:14DECOUPLING40C1374.7UF4.7UFC136C1314.7UF4.7UFC1394.7UFC1344.7UFC135C1414.7UF4.7UFC132C1384.7UFC1334.7UFC3600.1UF0.1UFC3590.1UFC362 C3610

3-20-2000_10:14BULK DECOUPLING410.1UFC256 C2570.1UF0.1UFC258C2550.1UF100UFC246C249100UF100UFC250C251100UF100UFC243 C237100UF100UFC236C2350.1UF22UFC265

3-20-2000_10:14REVISION HISTORY42DRAWN BY:LAST REVISED: SHEET:FOLSOM, CALIFORNIA 956301900 PRAIRIE CITY ROAD87 6 54 32 1ABCD12345678DCBAPCG PLATFORM D

43TEST_CLK665HL77,8HL67,8HL57,8HL47,8HL87,8HL107,8HL_STB#7,8HL_STB7,8HL97,8HL37,8HL27,8HL17,8HL07,86,8HUBREFJ26115048421816141210864644424038363432302

Intel® 820E Chipset R 24 Design Guide Figure 4. (A-C) AC’97 Connections 4A. AC'97 with Audio Codecs (4-Channel Secondary)4B. AC'97 wi

Intel® 820E Chipset R Design Guide 25 1.4.10. Low-Pin-Count (LPC) Interface In the Intel 820E chipset platform, the super I/O component has m

Intel® 820E Chipset R 26 Design Guide This page is intentionally left blank.

Intel® 820E Chipset R Design Guide 27 2. Layout/Routing Guidelines This chapter documents the motherboard layout and routing guidelines for In

Intel® 820E Chipset R 28 Design Guide Figure 5. MCH 324-Ball µBGA* CSP Quadrant Layout (Top View) mch_quadAGP 2.0 Hub interface System bus Sys

Intel® 820E Chipset R Design Guide 29 2.3. Intel® 820E Chipset Component Placement Notes: 1. The ATX and NLX placements and layouts shown in

Intel® 820E Chipset R Design Guide 3 Contents 1. Introduction ...

Intel® 820E Chipset R 30 Design Guide 2.4. Core Chipset Routing Recommendations The following two figures show MCH core routing examples: Figu

Intel® 820E Chipset R Design Guide 31 Figure 9. Secondary-Side MCH Core Routing Example (ATX)

Intel® 820E Chipset R 32 Design Guide 2.5. Source-Synchronous Strobing A technology used in AGP 4×, Direct RDRAM and the hub interface, source-

Intel® 820E Chipset R Design Guide 33 Table 2. AGP 2× Data/Strobe Association Data Associated Strobe AD[15:0] and C/BE[1:0]# AD_STB0 AD[31:16

Intel® 820E Chipset R 34 Design Guide Because of the tolerances of components such as PCBs, connectors, and termination resistors, there will b

Intel® 820E Chipset R Design Guide 35 2.7.2.1. RSL Routing The RSL signals enter the first RIMM on the left side, propagate through the RIMM,

Intel® 820E Chipset R 36 Design Guide The following figure shows a top view of the trace width/spacing requirements for the RSL signals. Figure

Intel® 820E Chipset R Design Guide 37 Figure 16. Secondary-Side RSL Breakout Example

Intel® 820E Chipset R 38 Design Guide 2.7.2.2. RSL Termination All RSL signals must be terminated to 1.8 V (VTERM) using 27-Ω 1% or 28 Ω 2% res

Intel® 820E Chipset R Design Guide 39 Figure 18. Direct RDRAM* Termination Example 2.7.2.3. Direct RDRAM* Ground Plane Reference All RSL sig

Intel® 820E Chipset R 4 Design Guide 2.8.3. 2×/4× Timing Domain Routing Guidelines ...62 2.8.4

Intel® 820E Chipset R 40 Design Guide Figure 19. Incorrect Direct RDRAM* Ground Plane Referencing 3.3-V Plane1.8-V PlaneMCHWrongdir_Rambus_gnd_

Intel® 820E Chipset R Design Guide 41 All four layers of the motherboard require correct grounding between the RSL signals on the motherboard,

Intel® 820E Chipset R 42 Design Guide Table 4. Copper Tab Area Calculation Dielectric Thickness (D) Separation between Signal Trace and Copper

Intel® 820E Chipset R Design Guide 43 Figure 21. Connector Compensation Example

Intel® 820E Chipset R 44 Design Guide Figure 22. Section A (See Note), Top Layer Note: Refer to Figure 21. For clarity, the ground flood was

Intel® 820E Chipset R Design Guide 45 Figure 23. Section A (See Note), Bottom Layer Note: Refer to Figure 21. For clarity, the ground flood

Intel® 820E Chipset R 46 Design Guide Figure 24. Section B (See Note), Top Layer Note: Refer to Figure 21. For clarity, the ground flood was

Intel® 820E Chipset R Design Guide 47 Figure 25. Section B (See Note), Bottom Layer Note: Refer to Figure 21. For clarity, the ground flood

Intel® 820E Chipset R 48 Design Guide The copper tab area for the recommended stack-up was determined by means of simulation. The amount of cap

Intel® 820E Chipset R Design Guide 49 The CTAB can be implemented on the multiple layers to minimize routing and space constraints. Figure 28

Intel® 820E Chipset R Design Guide 5 2.22. LAN Layout Guidelines...

Intel® 820E Chipset R 50 Design Guide Figure 29. RSL Signal Layer Alternation MCHSignal on secondary sideSignal on primary sideSignal ASignal B

Intel® 820E Chipset R Design Guide 51 All RSL signals must satisfy the following equation: Equation 2. RDRAM RSL Signal Trace Length Calculati

Intel® 820E Chipset R 52 Design Guide It is necessary to compensate for the slight difference in electrical characteristics between a dummy via

Intel® 820E Chipset R Design Guide 53 Table 8. Line Matching and Via Compensation Example1,2,3,4,5,6,7,8,9,10 Signal Ball on MCH Nominal RSL L

Intel® 820E Chipset R 54 Design Guide 2.7.3. Direct RDRAM* Reference Voltage The Direct RDRAM reference voltage (RAMREF) must be generated as

Intel® 820E Chipset R Design Guide 55 Figure 33. High-Speed CMOS Termination high_spd_cmos_termMCHRIMM_0RIMM_191 ΩVterm39 ΩR1R2 2.7.4.1. SIO R

Intel® 820E Chipset R 56 Design Guide 2.7.4.2. Suspend-to-RAM Shunt Transistor When an Intel 820E chipset system enters or exits Suspend to RA

Intel® 820E Chipset R Design Guide 57 2.7.5. Direct RDRAM* Clock Routing Refer to Chapter 4 Clocking for the Intel 820E chipset platform’s Di

Intel® 820E Chipset R 58 Design Guide  If any RSL signals are routed, even for a short distance, out of the last RIMM (towards termination) o

Intel® 820E Chipset R Design Guide 59  All RSL signals are routed adjacent to a ground reference plane. This includes all signals from the l

Intel® 820E Chipset R 6 Design Guide 3.2.3. Pre-Layout Simulation...

Intel® 820E Chipset R 60 Design Guide 2.8. AGP 2.0 For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), ref

Intel® 820E Chipset R Design Guide 61 Signal Groups • 1× timing domain  CLK (3.3 V)  RBF#  WBF#  ST[2:0]  PIPE#  REQ#  GNT# 

Intel® 820E Chipset R 62 Design Guide Table 10. AGP 2.0 Data/Strobe Associations Data Associated Strobe in 1× Associated Strobe in 2× Associa

Intel® 820E Chipset R Design Guide 63 5.8 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be 4.2 inches long, and the data si

Intel® 820E Chipset R 64 Design Guide The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the sourc

Intel® 820E Chipset R Design Guide 65 2.8.5. AGP Clock Routing The maximum total AGP clock skew (between the MCH and the graphics component)

Intel® 820E Chipset R 66 Design Guide Figure 37. Top Signal Layer Ground Reference It is strongly recommended that, at a minimum, the followin

Intel® 820E Chipset R Design Guide 67 Note: The motherboard provides 3.3 V to the VCC pins of the AGP connector. If the graphics controller n

Intel® 820E Chipset R 68 Design Guide Figure 38. AGP VDDQ Generation Example Circuit SHDN IPOSVIN

Intel® 820E Chipset R Design Guide 69 During a 3.3 V AGP 2.0 operation, VREF must be 0.4 VDDQ. However, during a 1.5 V AGP 2.0 operation, VREF

Intel® 820E Chipset R Design Guide 7 4.8. Decoupling Recommendation for CK133 and DRCG ... 174

Intel® 820E Chipset R 70 Design Guide 2.8.9. Compensation The MCH AGP interface supports resistive buffer compensation (RCOMP). Tie the GRCOMP

Intel® 820E Chipset R Design Guide 71 2.8.10.1. AGP Signal Voltage Tolerance List The following signals on the AGP interface are 3.3 V tolera

Intel® 820E Chipset R 72 Design Guide 2.8.12. AGP Universal Retention Mechanism (RM) Environmental testing and field reports indicate that, wi

Intel® 820E Chipset R Design Guide 73 Figure 41. AGP Left-Handed RM Keep-Out Information Recommended for all AGP cards, the AGP RM is detaile

Intel® 820E Chipset R 74 Design Guide 2.9. Hub Interface The MCH and ICH2 ballout assignments have been optimized to simplify the hub interface

Intel® 820E Chipset R Design Guide 75 2.9.1. 8-Bit Hub Interface Routing Guidelines This section documents the routing guidelines for the 8-b

Intel® 820E Chipset R 76 Design Guide Table 16. 8-Bit Hub Interface HUBREF Generation Circuit Specifications Buffer Mode HUBREF Voltage Specif

Intel® 820E Chipset R Design Guide 77 2.9.1.4. 8-Bit Hub Interface Compensation The hub interface uses a compensation signal to adjust buffer

Intel® 820E Chipset R 78 Design Guide 2.10.1. System Bus Ground Plane Reference All system bus signals must be referenced to GND to provide th

Intel® 820E Chipset R Design Guide 79 Additional Considerations • Distribute VTT with a wide trace. A 0.050 inch minimum trace is recommended

Intel® 820E Chipset R 8 Design Guide Figures Figure 1. Intel® 820E Chipset Platform Performance Desktop Block Diagram ...1

Intel® 820E Chipset R 80 Design Guide 2.12.1. Cable Detection for Ultra ATA/66 and Ultra ATA/100 The ICH2 IDE controller supports PIO, multiwo

Intel® 820E Chipset R Design Guide 81 Figure 46. Combination Host-Side/Device-Side IDE Cable Detection 80-conductorIDE cableIDE drive5 VICH2GP

Intel® 820E Chipset R 82 Design Guide 2.12.3. Device-Side Cable Detection For platforms that must implement device-side detection only (e.g.,

Intel® 820E Chipset R Design Guide 83 2.12.4. Primary IDE Connector Requirements Figure 48. Connection Requirements for Primary IDE Connecto

Intel® 820E Chipset R 84 Design Guide 2.12.5. Secondary IDE Connector Requirements Figure 49. Connection Requirements for Secondary IDE Connec

Intel® 820E Chipset R Design Guide 85 2.13. AC’97 The ICH2 implements an AC’97 2.1-compliant digital controller. Any codec attached to the ICH

Intel® 820E Chipset R 86 Design Guide Clocking is provided from the primary codec on the link via BITCLK, and is derived from a 24.576 MHz crys

Intel® 820E Chipset R Design Guide 87 Figure 51. CDC_DN_ENAB# Support Circuitry for a Single Codec on Motherboard Codec ARESET#SDATA_INCodec

Intel® 820E Chipset R 88 Design Guide Figure 52. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade PrimaryAudioCodecRESET#SDATA_IN

Intel® 820E Chipset R Design Guide 89 Figure 54. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard / Two-Codecs on CNR Codec ARESET

Intel® 820E Chipset R Design Guide 9 Figure 47. Device-Side IDE Cable Detection ...

Intel® 820E Chipset R 90 Design Guide Valid Codec Configurations Table 19. Codec Configurations Valid Codec Configurations Invalid Codec Confi

Intel® 820E Chipset R Design Guide 91 2.13.3. AC’97 Routing To ensure the maximum performance of the codec, proper component placement and rou

Intel® 820E Chipset R 92 Design Guide 2.13.4. Motherboard Implementation The following design considerations are provided for the implementatio

Intel® 820E Chipset R Design Guide 93 Figure 56. USB Data Signals 15k15k15 ΩΩΩΩ 15 ΩΩΩΩ ICH2 P+ P- USB Connector < 1" < 1" 90

Intel® 820E Chipset R 94 Design Guide 2.16. I/O APIC Design Recommendation UP systems not using the integrated I/O APIC should comply with the

Intel® 820E Chipset R Design Guide 95 Figure 57. SMBUS/SMLink Interface 82801BAICH2Host controllerslave interfaceSMBusSMBCLKSPD dataTemperatur

Intel® 820E Chipset R 96 Design Guide 2.18. PCI The ICH2 provides a PCI Bus interface that is compliant with the PCI Local Bus Specification, R

Intel® 820E Chipset R Design Guide 97 2.19.1. RTC Crystal The ICH2 RTC module requires an external 32.768 kHz oscillating source connected on

Intel® 820E Chipset R 98 Design Guide 2.19.3. RTC Layout Considerations • Minimize the RTC lead lengths. Approximately 0.25 inch is sufficien

Intel® 820E Chipset R Design Guide 99 A standby power supply should be used in a desktop system to provide continuous power to the RTC when av