Intel CM8063101049806 Arkusz Danych Pobierz pdf (Strona 47)

Intel

Itanium

Processor 9300 Series and 9500 Series Datasheet 47

Electrical Specifications

2.6.3.3 Cache Static and Transient Tolerances

Table 2-22 and Figure 2-12 specify static and transient tolerances for the cache

outputs.

170 VID - 0.145 VID - 0.165 VID - 0.185

175 VID - 0.149 VID - 0.169 VID - 0.189

180

Notes:

1. The V

CC_MIN

and V

CC_MAX

load lines represent static and transient limits.

2. This table is intended to aid in reading discrete points on

Figure 2-11.

3. The load lines specify voltage limits at the die measured at the V

CCCORESENSE

and V

SSCORESENSE

pins.

Voltage regulation feedback for voltage regulator circuits must be taken from processor V

and V

pins.

Refer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR

implementation.

4. V

(max)=VID-R

-4 mV;V

(nom)=VID-R

-19 mV;V

(min)=VID-R

-34mV; R

=0.85 mΩ.

Figure 2-11. V

CORE

Static and Transient Tolerance for Intel

Itanium

Processor 9300

Series

Table 2-21. V

CORE

Static and Transient Tolerance for Intel

Itanium

Processor 9300

Series (Sheet 2 of 2)

Core Current (A) Voltage Deviation from VID Setting (V)1,2,3,4

CC_CORE

CC_Max

CC_Typ

CC_Min

VccCORE Tolerance Bands

-0.20

-0.18

-0.16

-0.14

-0.12

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180

Icc (A)

Normalized Vcc (V)

AC max (V)

DC max (V)

Typical Vcc (V)

DC min (V)

AC min (V)

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 171 172

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