Intel CP80617004803AA Arkusz Danych Pobierz pdf (Strona 73)

Datasheet 73

Signal Description

6.2 Memory Reference and Compensation

SB_MA[15:0] Memory Address: These signals are used to

provide the multiplexed row and column

address to the SDRAM.

DDR3

SB_CK[1:0] SDRAM Differential Clock: Channel B

SDRAM Differential clock signal pair. The

crossing of the positive edge of SB_CK and

the negative edge of its complement

SB_CK# are used to sample the command

and control signals on the SDRAM.

DDR3

SB_CK#[1:0] SDRAM Inverted Differential Clock:

Channel B SDRAM Differential clock signal-

pair complement.

DDR3

SB_CKE[1:0] Clock Enable: (1 per rank) Used to:

- Initialize the SDRAMs during power-up.

- Power-down SDRAM ranks.

- Place all SDRAM ranks into and out of self-

refresh during STR.

DDR3

SB_CS#[1:0] Chip Select: (1 per rank) Used to select

particular SDRAM components during the

active state. There is one Chip Select for

each SDRAM rank.

DDR3

SB_ODT[1:0] On Die Termination: Active Termination

Control.

DDR3

Table 6-23.Memory Reference and Compensation

Signal Name Description

Direction/Buffer

Type

SM_RCOMP[2:0] System Memory Impedance

Compensation:.

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

Memory Channel A/B DIMM Voltage. O

Table 6-22.Memory Channel B (Sheet 2 of 2)

Signal Name Description

Direction/

Buffer Type

1 2 ... 68 69 70 71 72 73 74 75 76 77 78 ... 180 181

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