Intel CP80617004803AA Arkusz Danych Pobierz pdf (Strona 68)

Thermal Management

68 Datasheet

controller will shut off its internal clocks (thus halting program execution) in an attempt

to reduce the core junction temperature. Once activated, THERMTRIP# remains latched

until RSTIN# is asserted.

5.2.2.5 Render Thermal Throttling

Render Thermal Throttling of the integrated graphics and memory controller allows for

the reduction the render core engine frequency and voltage, thus reducing internal

graphics controller power and integrated graphics and memory controller thermals.

Performance is degraded, but the platform thermal burden is relieved.

Render Thermal Throttling using several frequency/voltage operating points that can be

used to throttle the render core. If the temperature of the integrated graphics and

memory controller internal DTS exceeds the Hot-trip point, the integrated graphics will

switch to a lower frequency/voltage operating point. After a timeout, the DTS is

rechecked, and if the DTS temperature is still greater than the designed hysteresis, the

integrated graphics will continue to switch to lower frequency/voltage operating points.

Once the DTS reports a temperature below the hysteresis value, the render clock

frequency and voltage will be restored to its pre-thermal event state.

Caution: The Render Thermal Throttling must be enabled for the product to remain within

specification.

5.2.3 Platform Environment Control Interface (PECI)

The Platform Environment Control Interface (PECI) is a one-wire interface that provides

a communication channel between Intel processor and chipset components to external

monitoring devices. The processor implements a PECI interface to allow communication

of processor thermal information to other devices on the platform. The processor

provides a digital thermal sensor (DTS) for fan speed control. The DTS is calibrated at

the factory to provide a digital representation of relative processor temperature.

Averaged DTS values are read via the PECI interface.

The PECI physical layer is a self-clocked one-wire bus that begins each bit with a

driven, rising edge from an idle level near zero volts. The duration of the signal driven

high depends on whether the bit value is a Logic 0 or Logic 1. PECI also includes

variable data transfer rate established with every message. The single wire interface

provides low board routing overhead for the multiple load connections in the congested

routing area near the processor and chipset components. Bus speed, error checking,

and low protocol overhead provides adequate link bandwidth and reliability to transfer

critical device operating conditions and configuration information.

5.2.3.1 Fan Speed Control with Digital Thermal Sensor

Digital Thermal Sensor based fan speed control (T

FAN

) is a recommended feature to

achieve optimal thermal performance. At the T

FAN

temperature, Intel recommends full

cooling capability well before the DTS reading reaches T

j,max

. An example of this would

be T

FAN

= T

j,max

- 10ºC.

1 2 ... 63 64 65 66 67 68 69 70 71 72 73 ... 180 181

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