Intel CM8064401548605 Arkusz Danych

Intel® Xeon® Processor E5-1600 andE5-2600 v3 Product Families,Volume 1 of 2, ElectricalDatasheetSeptember 2014Order No.: 330783-001

Document Document Number/LocationIntel® 64 and IA-32 Architectures Optimization Reference ManualIntel® Virtualization Technology Specification for Dir

Pin Name Pin NumberBufferType DirectionVSS DA9 GND VSS DB12 GND VSS DB34 GND VSS DB40 GND VSS DB58 GND VSS DB6 GND VSS DC5 GND VSS DC53 GND VSS DC5

Pin Name Pin NumberBufferType DirectionVSS G39 GND VSS G41 GND VSS G45 GND VSS G47 GND VSS G49 GND VSS G5 GND VSS G51 GND VSS G53 GND VSS G57 GND V

Pin Name Pin NumberBufferType DirectionVSS N23 GND VSS N27 GND VSS N29 GND VSS N33 GND VSS N35 GND VSS N37 GND VSS N39 GND VSS N43 GND VSS N45 GND

Pin Name Pin NumberBufferType DirectionVSS V12 GND VSS V36 GND VSS V44 GND VSS V46 GND VSS V48 GND VSS V50 GND VSS V52 GND VSS W23 GND VSS W27 GND

Term DescriptionIIO The Integrated I/O Controller. An I/O controller that is integrated inthe processor die.IMC The Integrated Memory Controller. A Me

Term DescriptionNID Node ID (NID) or NodeID (NID). The processor implements up to 4-bits of NodeID (NID).NodeID Node ID (NID) or NodeID (NID).pcode Pc

Term DescriptionTSOD Temperature Sensor On DIMMUDIMM Unbuffered Dual In-line Memory ModuleUncore The portion of the processor comprising the shared LL

2.0 Electrical SpecificationsThis chapter describes processor signaling, DC specifications, and signal quality.References to various interfaces (memo

DMI2/PCI Express SignalsThe Direct Media Interface Gen 2 (DMI2) sends and receives packets and/orcommands to the PCH. The DMI2 is an extension of the

System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)The processor Core, processor Uncore, Intel® QuickPath Interconnect link, PCIExpress* and DDR4 mem

Power, Ground and Sense SignalsProcessors also include various other signals, including power / ground and sensepoints. Details can be found in Table

The processor uses voltage identification signals to support automatic selection ofVCCIN power supply voltage. If the processor socket is empty (SKTOC

SetVID DecayThe SetVID_Decay command is the slowest of the DVID transitions. It is normallyused for VID down transitions. The VR does not control the

By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below.You may not use or facilitate the use

Figure 2. VR Power State TransitionsPS1PS0PS2SVID Voltage Rail AddressingThe processor addresses 3 different voltage rail control segments within VR12

PWM Address (HEX) Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families4. For future platform flexibility, the VR controller should include a

HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN52 1.31 75 1.66 98 2.01 BB 2.36 DE 2.7153 1.320 76 1.67 99 2.02 BC 2.37 DF 2.7254 1.33 77 1

Table 6. Signal Description Buffer TypesSignal DescriptionAnalog Analog reference or output. May be used as a threshold voltage or for buffercompensat

Differential/Single Ended Buffer Type SignalDDR4 Data SignalsDifferential SSTL Input/Output DDR{0/1/2/3}_DQS_D[N/P][17:0]Single ended SSTL Input/Outpu

Differential/Single Ended Buffer Type SignalDifferential Intel® QPI Input QPI{0/1}_DRX_D[N/P][19:0]QPI{0/1}_CLKRX_D[N/P]Intel® QPI Output QPI{0/1}_DTX

Differential/Single Ended Buffer Type SignalCMOS 1.05V Input EAR_NOutput SKTOCC_NPower/Other SignalsPower / Ground VCCIN, VCCD_01, VCCD_23, VCCIO_IN,V

Table 9. Power-On Configuration Option LandsConfiguration Option Land Name NotesOutput tri state PROCHOT_N 1Execute BIST (Built-In Self Test) BIST_ENA

Output Tri-State Signal Groups SignalsQPI1_DTX_DP[19:00]PCI Express* PE1A_TX_DN[3:0]PE1A_TX_DP[3:0]PE1B_TX_DN[7:4]PE1B_TX_DP[7:4]PE2A_TX_DN[3:0]PE2A_T

Note: All processors within a system must run at a common maximum non-Turbo ratio. Thesystem BIOS may be required to program the FLEX_RATIO register

Revision HistoryDocumentNumberRevisionNumberDescription Date330783 001 Initial release September 2014Revision History—Intel® Xeon® Processor E5-1600 a

Symbol Parameter Min Max Unit2. Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Overshoot/Undershoot To

DC SpecificationsDC specifications are defined at the processor pads, unless otherwise noted.DC specifications are only valid while meeting specificat

Figure 3. Serial VID Interface (SVID) Signals Clock TimingsSVIDCLK@ cpu padSVIDDATA(drive) @ cpu padvalidSVIDDATA(recive) @ cpu padvalid(combine dr &

SegmentTDPICCIN_MAX @ VCCIN(A)ICC_ MAX @ VCCIO_ IN (A)ICC_ MAX @ VCCPECI (A)ICCD01_ MAX (A)5ICCD23_ MAX (A)5ICCIN_ TDC3 @ VCCIN(A)ICC_ TDC3 @ VCCIO_ I

ICCIN (A) VCCIN_Max (V) VCCIN_Nom (V) VCCIN_Min (V) Notes50 VID - 0.031 VID - 0.053 VID - 0.07560 VID - 0.041 VID - 0.063 VID - 0.08570 VID - 0.052 VI

Figure 4. VCCIN Static and Transient Tolerance Loadlines-0.280-0.260-0.240-0.220-0.200-0.180-0.160-0.140-0.120-0.100-0.080-0.060-0.040-0.0200.0000.020

Figure 5. VCCIN Overshoot Example Waveform0 5 10 15 20 25 30Voltage [V] Time [us] VID + VOS_MAX TOS_MAX VOS_MAX VCCIN_MAX (I1) VCCIN_MAX + VOS_MAX V

Symbol Parameter Min Nom Max Units Notes1VOLOutput Low Voltage Varies 10VOHOutput High Voltage VCCDReference Clock SignalR ONDDR4 Clock BufferOn Resis

PECI DC SpecificationsSymbol Definition andConditionsMin Max Units Figure Notes1VInInput Voltage Range -0.150 VCCPECI +0.150VVHysteresisHysteresis 0.1

Symbol Parameter Signal Min Max Unit Figure Notes1Vcross (rel) Relative CrossingPointSingle Ended 0.250 + 0.5*(VHavg - 0.700)0.550 + 0.5*(VHavg - 0.70

ContentsRevision History...31.0 Introdu

Figure 7. BCLK{0/1} Differential Clock Crosspoint Specification660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 85020025030

Symbol Parameter Min Max Units NotesILLeakage Current Signals 50 200 µAOutput Edge Rate(50 ohm to VCCIO_IN, between VIL and VIH)0.05 0.6 V/ns 1Note: 1

Processor Asynchronous Sideband DC SpecificationsSymbol Parameter Min Max Units NotesCMOS1.05v SignalsVIL_CMOS1.05VInput Low Voltage 0.4*V CCIO_INV 1,

Segment Model Number TDP C1E (W) 2C3 (W) 2C6 (W)SegmentOptimizedE5-2699 v3 145W 18-Core 56 36 14E5-2698 v3 135W 16-Core 47 33 14E5-2697 v3 145W 14-Cor

Signal QualityData transfer requires the clean reception of data signals and clock signals. Ringingbelow receiver thresholds, non-monotonic signal edg

Table 17. Processor I/O Overshoot/Undershoot SpecificationsSignal Group MaximumUndershootMaximumOvershootOvershootDurationUndershootDurationNotesIntel

Overshoot/Undershoot Pulse DurationPulse duration describes the total amount of time that an overshoot/undershoot eventexceeds the overshoot/undershoo

Reading Overshoot/Undershoot Specification TablesThe overshoot/undershoot specification for the processor is not a simple single value.Instead, many f

3.0 Processor Land ListingRefer to Appendix A in this document.Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Processor Land ListingI

4.0 Intel® Xeon® Processor E5-1600 and E5-2600 v3Product Families Signal DescriptionsThis chapter describes the Intel® Xeon® processor E5-1600 and E5

4.6 System Reference Clock Signals...524.7 JTAG and TAP Signals...

Signal Name DescriptionDDR{0/1/2/3}_ODT[5:0] On Die Termination. Enables DRAM on die termination during Data Write orData Read transactions.DDR{0/1/2/

Signal Name DescriptionPE2C_RX_DN[11:8]PE2C_RX_DP[11:8]PCIe Receive Data InputPE2D_RX_DN[15:12]PE2D_RX_DP[15:12]PCIe Receive Data InputPE2A_TX_DN[3:0]

DMI2/PCI Express Port 0 SignalsTable 25. DMI2 and PCI Express Port 0 SignalsSignal Name DescriptionDMI_RX_DN[3:0]DMI_RX_DP[3:0]DMI2 Receive Data Input

JTAG and TAP SignalsTable 29. JTAG and TAP SignalsSignal Name DescriptionBPM_N[7:0] Breakpoint and Performance Monitor Signals: I/O signals from thepr

Signal Name Description• 0 = Hardware correctable error (no operating system or firmware actionnecessary)• 1 = Non-fatal error (operating system or fi

Signal Name DescriptionPWRGOOD PWRGOOD is a processor input. The processor requires this signal to be aclean indication that all processor clocks and

Signal Name DescriptionThis signal is pulled down on the die, refer to Table 8 on page 26 fordetails.EAR_N External Alignment of Reset, used to bring

Signal Name Description1 = Default. The platform is Intel TXT enabled. All sockets should be set toone. In a non-Scalable DP platform this is the defa

Appendix A: Pin ListAppendix A: Pin ListSeptember 2014 Order No: 330783-001Intel(R) Xeon(R) Processor E5-1600 and E5-2600 v3 Product Families, Vol. 1

Pin Name Pin NumberBufferType DirectionBCLK0_DN CN41 CMOS IBCLK0_DP CL41 CMOS IBCLK1_DN AW45 CMOS IBCLK1_DP BA45 CMOS IBIST_ENABLE AJ43 CMOS IBMCIN

Figures1 Input Device Hysteresis...152 VR Power State Transit

Pin Name Pin NumberBufferType DirectionDDR0_CS_N[3]/CID[1] CC25 SSTL ODDR0_CS_N[4] CK22 SSTL ODDR0_CS_N[5] CH24 SSTL ODDR0_CS_N[6]/CID[3] CH26 SSTL

Pin Name Pin NumberBufferType DirectionDDR0_DQ[43] CB32 SSTL I/ODDR0_DQ[44] CE27 SSTL I/ODDR0_DQ[45] CC27 SSTL I/ODDR0_DQ[46] CE31 SSTL I/ODDR0_DQ[

Pin Name Pin NumberBufferType DirectionDDR0_DQS_DP[1] BV12 SSTL I/O DDR0_DQS_DP[10] BU13 SSTL I/O DDR0_DQS_DP[11] CG9 SSTL I/O DDR0_DQS_DP[12] CG13

Pin Name Pin NumberBufferType DirectionDDR0_ODT[2] CJ23 SSTL O DDR0_ODT[3] CC23 SSTL O DDR0_ODT[4] CF24 SSTL O DDR0_ODT[5] CE25 SSTL O DDR0_PAR CK2

Pin Name Pin NumberBufferType DirectionDDR1_DQ[16] CR3 SSTL I/ODDR1_DQ[17] CV2 SSTL I/ODDR1_DQ[18] CT6 SSTL I/ODDR1_DQ[19] CP6 SSTL I/ODDR1_DQ[2] C

Pin Name Pin NumberBufferType DirectionDDR1_DQ[57] DF36 SSTL I/O DDR1_DQ[58] DC39 SSTL I/O DDR1_DQ[59] DA39 SSTL I/O DDR1_DQ[6] CA1 SSTL I/O DDR1_D

Pin Name Pin NumberBufferType DirectionDDR1_DQS_DP[8] DB14 SSTL I/O DDR1_DQS_DP[9] BV2 SSTL I/O DDR1_ECC[0] CU13 SSTL I/O DDR1_ECC[1] CV14 SSTL I/O

Pin Name Pin NumberBufferType DirectionDDR2_CKE[3] Y22 SSTL O DDR2_CKE[4] AB22 SSTL O DDR2_CKE[5] AD22 SSTL O DDR2_CLK_DN[0] W17 SSTL O DDR2_CLK_DN

Pin Name Pin NumberBufferType DirectionDDR2_DQ[30] V24 SSTL I/O DDR2_DQ[31] T24 SSTL I/O DDR2_DQ[32] N9 SSTL I/O DDR2_DQ[33] K8 SSTL I/O DDR2_DQ[34

Pin Name Pin NumberBufferType DirectionDDR2_DQS_DN[13] L7 SSTL I/O DDR2_DQS_DN[14] W9 SSTL I/O DDR2_DQS_DN[15] AJ15 SSTL I/O DDR2_DQS_DN[16] AJ9 SS

Tables1 Structure of the Processor Datasheet... 92 Public Publications...

Pin Name Pin NumberBufferType DirectionDDR2_MA[14] Y14 SSTL O DDR2_MA[15] R13 SSTL O DDR2_MA[16] P14 SSTL O DDR2_MA[17] T14 SSTL O DDR2_MA[2] T18 S

Pin Name Pin NumberBufferType DirectionDDR3_CS_N[4] A15 SSTL O DDR3_CS_N[5] F14 SSTL O DDR3_CS_N[6]/CID[3] G11 SSTL O DDR3_CS_N[7]/CID[4] A11 SSTL

Pin Name Pin NumberBufferType DirectionDDR3_DQ[44] C9 SSTL I/O DDR3_DQ[45] A9 SSTL I/O DDR3_DQ[46] D6 SSTL I/O DDR3_DQ[47] G7 SSTL I/O DDR3_DQ[48]

Pin Name Pin NumberBufferType DirectionDDR3_DQS_DP[10] C35 SSTL I/O DDR3_DQS_DP[11] J33 SSTL I/O DDR3_DQS_DP[12] F26 SSTL I/O DDR3_DQS_DP[13] M4 SS

Pin Name Pin NumberBufferType DirectionDDR3_ODT[3] D12 SSTL O DDR3_ODT[4] E13 SSTL O DDR3_ODT[5] E11 SSTL O DDR3_PAR J15 SSTL O DEBUG_EN_N F40 CMOS

Pin Name Pin NumberBufferType DirectionPE1A_TX_DN[3] J45 PCIEX3 O PE1A_TX_DP[0] K42 PCIEX3 O PE1A_TX_DP[1] L43 PCIEX3 O PE1A_TX_DP[2] K44 PCIEX3 O

Pin Name Pin NumberBufferType DirectionPE2B_TX_DN[4] AG53 PCIEX3 O PE2B_TX_DN[5] AH54 PCIEX3 O PE2B_TX_DN[6] AN53 PCIEX3 O PE2B_TX_DN[7] AP54 PCIEX

Pin Name Pin NumberBufferType DirectionPE3A_RX_DP[1] AJ45 PCIEX3 I PE3A_RX_DP[2] AH46 PCIEX3 I PE3A_RX_DP[3] AC49 PCIEX3 I PE3A_TX_DN[0] H50 PCIEX3

Pin Name Pin NumberBufferType DirectionPE3D_RX_DN[14] AM46 PCIEX3 IPE3D_RX_DN[15] AN45 PCIEX3 IPE3D_RX_DP[12] AJ47 PCIEX3 IPE3D_RX_DP[13] AR47 PCIE

Pin Name Pin NumberBufferType DirectionQPI0_DRX_DN[8] BG57 QPI I QPI0_DRX_DN[9] BP56 QPI I QPI0_DRX_DP[0] BJ51 QPI I QPI0_DRX_DP[1] BH52 QPI I QPI0

1.0 IntroductionThe Datasheet provides descriptions of the Intel® Xeon® processor v3 product familiesregisters and Electrical specifications (includi

Pin Name Pin NumberBufferType DirectionQPI0_DTX_DP[11] CA51 QPI O QPI0_DTX_DP[12] BY48 QPI O QPI0_DTX_DP[13] BY50 QPI O QPI0_DTX_DP[14] CE47 QPI O

Pin Name Pin NumberBufferType DirectionQPI1_DRX_DP[12] CV56 QPI I QPI1_DRX_DP[13] CU57 QPI I QPI1_DRX_DP[14] CT58 QPI I QPI1_DRX_DP[15] CM56 QPI I

Pin Name Pin NumberBufferType DirectionQPI1_DTX_DP[17] CT48 QPI O QPI1_DTX_DP[18] CT46 QPI O QPI1_DTX_DP[19] CT44 QPI O QPI1_DTX_DP[2] CU41 QPI O Q

Pin Name Pin NumberBufferType DirectionRSVD BF44RSVD BT44RSVD CA43RSVD BV44RSVD BY44RSVD DE53RSVD C53RSVD F56RSVD D56RSVD K58RSVD H58RSVD AU55RSVD

Pin Name Pin NumberBufferType DirectionRSVD CN43RSVD CL43SAFE_MODE_BOOTBK56 CMOS ISKTOCC_N BU49 NA OSOCKET_ID[0] CP52 CMOS ISOCKET_ID[1] CC53 CMOS

Pin Name Pin NumberBufferType DirectionVCCD_01 DB18 PWR VCCD_01 DB20 PWR VCCD_01 DB22 PWR VCCD_01 DB24 PWR VCCD_01 DB26 PWR VCCD_01 DE17 PWR VCCD_2

Pin Name Pin NumberBufferType DirectionVCCIN AN11 PWR VCCIN AN17 PWR VCCIN AP10 PWR VCCIN AP12 PWR VCCIN AP14 PWR VCCIN AP16 PWR VCCIN AP2 PWR VCCI

Pin Name Pin NumberBufferType DirectionVCCIN AW1 PWR VCCIN AY42 PWR VCCIN BA1 PWR VCCIN BA11 PWR VCCIN BA13 PWR VCCIN BA15 PWR VCCIN BA17 PWR VCCIN

Pin Name Pin NumberBufferType DirectionVCCIN BE9 PWR VCCIN BG1 PWR VCCIN BH10 PWR VCCIN BH12 PWR VCCIN BH14 PWR VCCIN BH16 PWR VCCIN BH2 PWR VCCIN

Pin Name Pin NumberBufferType DirectionVCCIN BM8 PWR VCCIN BN11 PWR VCCIN BN13 PWR VCCIN BN15 PWR VCCIN BN17 PWR VCCIN BN3 PWR VCCIN BN5 PWR VCCIN

Structure and ScopeThe following table summarizes the structure and scope of each volume of theprocessor Datasheet.Table 1. Structure of the Processor

Pin Name Pin NumberBufferType DirectionVSS AA55 GND VSS AA7 GND VSS AB12 GND VSS AB36 GND VSS AB40 GND VSS AB42 GND VSS AC11 GND VSS AC29 GND VSS A

Pin Name Pin NumberBufferType DirectionVSS AF26 GND VSS AF28 GND VSS AF30 GND VSSAF32 GND VSS AF34 GND VSS AF36 GND VSS AF38 GND VSS AF4 GND VSS AF

Pin Name Pin NumberBufferType DirectionVSS AL53 GND VSS AM10 GND VSS AM12 GND VSS AM14 GND VSS AM16 GND VSS AM2 GND VSS AM4 GND VSS AM56 GND VSS AM

Pin Name Pin NumberBufferType DirectionVSS AY10 GND VSS AY12 GND VSS AY14 GND VSS AY16 GND VSS AY2 GND VSS AY4 GND VSS AY44 GND VSS AY6 GND VSS AY8

Pin Name Pin NumberBufferType DirectionVSS BG47 GND VSS BG5 GND VSS BG7 GND VSS BG9 GND VSS BH58 GND VSS BJ55 GND VSS BJ57 GND VSS BK42 GND VSS BK4

Pin Name Pin NumberBufferType DirectionVSS BU45 GND VSS BU47 GND VSS BU5 GND VSS BU51 GND VSS BV10 GND VSS BV16 GND VSS BW15 GND VSS BW17 GND VSS B

Pin Name Pin NumberBufferType DirectionVSS CB40 GND VSS CB42 GND VSS CB44 GND VSS CB46 GND VSS CB48 GND VSS CB50 GND VSS CB52 GND VSS CB54 GND VSS

Pin Name Pin NumberBufferType DirectionVSS CH12 GND VSS CH30 GND VSS CH34 GND VSS CH36 GND VSS CH38 GND VSS CH40 GND VSS CH42 GND VSS CH44 GND VSS

Pin Name Pin NumberBufferType DirectionVSS CN3 GND VSS CN31 GND VSS CN33 GND VSS CN35 GND VSS CN37 GND VSS CN39 GND VSS CN5 GND VSS CN53 GND VSS CN

Pin Name Pin NumberBufferType DirectionVSS CW1 GND VSS CW15 GND VSS CW27 GND VSS CW29 GND VSS CW31 GND VSS CW33 GND VSS CW35 GND VSS CW37 GND VSS C