Intel 815 Instrukcja Użytkownika Strona 1

Intel® 815 Chipset Platform For Use with Universal Socket 370 Design Guide April 2001 Document Number: 298349-001R

R 10 Intel® 815 Chipset Platform Design Guide Tables Table 1. Processor Considerations for Universal Socket 370 Design...

AGP/Display Cache Design Guidelines R 100 Intel® 815 Chipset Platform Design Guide 7.8.2 Display Cache Clocking The display cache is clocked sou

Integrated Graphics Display Output R Intel® 815 Chipset Platform Design Guide 101 8 Integrated Graphics Display Output 8.1 Analog RGB/CRT 8.1

Integrated Graphics Display Output R 102 Intel® 815 Chipset Platform Design Guide Figure 49. Schematic of RAMDAC Video Interface RAMDACVCCDACA1/V

Integrated Graphics Display Output R Intel® 815 Chipset Platform Design Guide 103 8.1.2 Reference Resistor (Rset) Calculation The full-swing

Integrated Graphics Display Output R 104 Intel® 815 Chipset Platform Design Guide Figure 51 shows the recommended RAMDAC component placement and

Integrated Graphics Display Output R Intel® 815 Chipset Platform Design Guide 105 Figure 52. Recommended RAMDAC Reference Resistor Placement a

Integrated Graphics Display Output R 106 Intel® 815 Chipset Platform Design Guide 8.2 Digital Video Out The Digital Video Out (DVO) port is a sc

Hub Interface R Intel® 815 Chipset Platform Design Guide 107 9 Hub Interface The GMCH ball assignment and the ICH ball assignment have been op

Hub Interface R 108 Intel® 815 Chipset Platform Design Guide 9.1.1 Data Signals Hub interface data signals should be routed with a trace width of

Hub Interface R Intel® 815 Chipset Platform Design Guide 109 Figure 54. Single-Hub-Interface Reference Divider Circuit HUBREFHUBREFGMCHICHhub_

R Intel® 815 Chipset Platform Design Guide 11 Revision History Rev. No. Description Date -001 Initial Release. April 2001

Hub Interface R 110 Intel® 815 Chipset Platform Design Guide This page is intentionally left blank.

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 111 10 I/O Subsystem This chapter provides guidelines for connecting and routing the

I/O Subsystem R 112 Intel® 815 Chipset Platform Design Guide Figure 56. IDE Minimum/Maximum Routing and Cable Lengths 10-18 in.4-6 in.5-12 in.8 i

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 113 10.2 Cable Detection for Ultra ATA/66 An 80-conductor IDE cable is required for

I/O Subsystem R 114 Intel® 815 Chipset Platform Design Guide 10.2.1 Host Side Cable Detection BIOS Detects Cable Type Using GPIOs Host-side dete

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 115 10.2.2 Device Side Cable Detection BIOS Queries IDE Device for Cable Type Device

I/O Subsystem R 116 Intel® 815 Chipset Platform Design Guide 10.2.3 Primary IDE Connector Requirements Figure 60. Resistor Schematic for Primary

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 117 10.2.4 Secondary IDE Connector Requirements Figure 61. Resistor Schematic for Se

I/O Subsystem R 118 Intel® 815 Chipset Platform Design Guide 10.2.5 Layout for Both Host-Side and Device-Side Cable Detection The Intel 815 chip

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 119 10.3 AC’97 The ICH implements an AC’97 2.1-compliant digital controller. Any code

R 12 Intel® 815 Chipset Platform Design Guide This page is intentionally left blank.

I/O Subsystem R 120 Intel® 815 Chipset Platform Design Guide The basic recommendations are as follows: • Special consideration must be given for

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 121 10.3.2 AC’97 Signal Quality Requirements In a lightly loaded system (e.g., singl

I/O Subsystem R 122 Intel® 815 Chipset Platform Design Guide 10.4 Using Native USB Interface The following are general guidelines for the native

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 123 Figure 63. Recommended USB Schematic 15 kΩ15 kΩ15 Ω15 Ω47 pF47 pFICHP+P-USB conne

I/O Subsystem R 124 Intel® 815 Chipset Platform Design Guide 10.6 SMBus The Alert on LAN signals can be used as: • Alert on LAN signals: 4.7 kΩ

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 125 10.8 LPC/FWH 10.8.1 In-Circuit FWH Programming All cycles destined for the FWH

I/O Subsystem R 126 Intel® 815 Chipset Platform Design Guide 10.9.1 RTC Crystal The ICH RTC module requires an external oscillating source of 32.

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 127 10.9.3 RTC Layout Considerations • Keep the RTC lead lengths as short as possib

I/O Subsystem R 128 Intel® 815 Chipset Platform Design Guide 10.9.5 RTC External RTCRESET Circuit The ICH RTC requires some additional external

I/O Subsystem R Intel® 815 Chipset Platform Design Guide 129 10.9.7 RTC Routing Guidelines • All RTC OSC signals (RTCX1, RTCX2, VBIAS) shoul

Introduction R Intel® 815 Chipset Platform Design Guide 13 1 Introduction This design guide organizes Intel’s design recommendations for the I

I/O Subsystem R 130 Intel® 815 Chipset Platform Design Guide This page is intentionally left blank.

Clocking R Intel® 815 Chipset Platform Design Guide 131 11 Clocking For an Intel 815 chipset platform, there are two clock specifications. One

Clocking R 132 Intel® 815 Chipset Platform Design Guide Figure 68. Platform Clock Architecture (2 DIMMs) GMCHCPU 2_ITPAPIC 0CPU 1CPU 02.5 VClock

Clocking R Intel® 815 Chipset Platform Design Guide 133 11.2 3-DIMM Clocking Table 29 shows the characteristics of the clock generator for a 3

Clocking R 134 Intel® 815 Chipset Platform Design Guide Figure 69. Universal Platform Clock Architecture (3 DIMMs) GMCHAPICCPU 1CPU 02.5 VCK 815

Clocking R Intel® 815 Chipset Platform Design Guide 135 11.3 Clock Routing Guidelines This section presents the generic clock routing guideli

Clocking R 136 Intel® 815 Chipset Platform Design Guide Table 30. Simulated Clock Routing Solution Space Destination Topology from Previous Figur

Clocking R Intel® 815 Chipset Platform Design Guide 137 11.4 Clock Decoupling Several general layout guidelines should be followed when laying

Clocking R 138 Intel® 815 Chipset Platform Design Guide 11.6 Clock Skew Assumptions The clock skew assumptions in the following table are used i

Clocking R Intel® 815 Chipset Platform Design Guide 139 11.7 Intel® CK-815 Power Gating On Wake Events For systems providing functionality wit

Introduction R 14 Intel® 815 Chipset Platform Design Guide 1.1 Terminology This section describes some of the terms used in this document. Additi

Clocking R 140 Intel® 815 Chipset Platform Design Guide This page is intentionally left blank.

Power Delivery R Intel® 815 Chipset Platform Design Guide 141 12 Power Delivery This chapter contains power delivery guidelines. Table 32 prov

Power Delivery R 142 Intel® 815 Chipset Platform Design Guide supplied by the power supply. Due to the requirements of main memory and the PCI 3.

Power Delivery R Intel® 815 Chipset Platform Design Guide 143 5V Dual Switch This switch will power the 5V Dual plane from the 5V core ATX sup

Power Delivery R 144 Intel® 815 Chipset Platform Design Guide Refer to Section 12.4.1 for more information on the power ramp sequence requirement

Power Delivery R Intel® 815 Chipset Platform Design Guide 145 A simplistic DC calculation for a pull-up value is: RMAX = (VCCPU MIN - VIH MIN)

Power Delivery R 146 Intel® 815 Chipset Platform Design Guide 12.3 Power Management Signals • A power button is required by the ACPI specificat

Power Delivery R Intel® 815 Chipset Platform Design Guide 147 12.3.1 Power Button Implementation The following items should be considered whe

Power Delivery R 148 Intel® 815 Chipset Platform Design Guide 12.4 1.85V/3.3V Power Sequencing This section shows the timings among various sign

Power Delivery R Intel® 815 Chipset Platform Design Guide 149 Figure 74. S0-S3-S0 Transition DRAM activeDRAM in STR (CKE low) DRAM activeClock

Introduction R Intel® 815 Chipset Platform Design Guide 15 Term Description Ringback The voltage that a signal rings back to after achieving

Power Delivery R 150 Intel® 815 Chipset Platform Design Guide Figure 75. S0-S5-S0 Transition DRAM activeDRAM in STR (CKE low) DRAM activeClocks v

Power Delivery R Intel® 815 Chipset Platform Design Guide 151 Table 33. Power Sequencing Timing Definitions Symbol Parameter Min. Max. Units t

Power Delivery R 152 Intel® 815 Chipset Platform Design Guide 12.4.1 VDDQ/VCC1_85 Power Sequencing For the consideration of long term component

Power Delivery R Intel® 815 Chipset Platform Design Guide 153 output buffers that are normally disabled, and the ICH may unexpectedly drive th

Power Delivery R 154 Intel® 815 Chipset Platform Design Guide 12.4.3 3.3V/V5REF Sequencing V5REF is the reference voltage for 5V tolerance on inp

System Design Checklist R Intel® 815 Chipset Platform Design Guide 155 13 System Design Checklist 13.1 Design Review Checklist Introduction

System Design Checklist R 156 Intel® 815 Chipset Platform Design Guide 13.2.2 CMOS Checklist Checklist Items Recommendations IERR# • 150 Ω pu

System Design Checklist R Intel® 815 Chipset Platform Design Guide 157 Checklist Items Recommendations CLKREF • Connect to divider on VCC2.

System Design Checklist R 158 Intel® 815 Chipset Platform Design Guide Checklist Items Recommendations NO CONNECTS • The following pins must b

System Design Checklist R Intel® 815 Chipset Platform Design Guide 159 13.3.2 Designs That Do Not Use the AGP Port Any external graphics impl

Introduction R 16 Intel® 815 Chipset Platform Design Guide 1.2 Reference Documents Document Document Number / Location Intel® 815 Chipset Family:

System Design Checklist R 160 Intel® 815 Chipset Platform Design Guide 13.3.3 System Memory Interface Checklist Checklist Items Recommendations

System Design Checklist R Intel® 815 Chipset Platform Design Guide 161 13.4 ICH Checklist 13.4.1 PCI Checklist Checklist Items Recommendati

System Design Checklist R 162 Intel® 815 Chipset Platform Design Guide 13.4.2 USB Checklist Checklist Items Recommendations USBP0P, USBP0N, US

System Design Checklist R Intel® 815 Chipset Platform Design Guide 163 13.4.4 IDE Checklist Checklist Items Recommendations PDCS3#, SDCS3#,

System Design Checklist R 164 Intel® 815 Chipset Platform Design Guide Checklist Items Recommendations PDD[15:0], PDIOW#, PDIOR#, PDREQ, PDDACK#

System Design Checklist R Intel® 815 Chipset Platform Design Guide 165 13.5 LPC Checklist Checklist Items Recommendations RCIN# • Pull-up

System Design Checklist R 166 Intel® 815 Chipset Platform Design Guide 13.6 System Checklist Checklist Items Recommendations KEYLOCK# • Pull-

System Design Checklist R Intel® 815 Chipset Platform Design Guide 167 13.8 Clock Synthesizer Checklist Checklist Items Recommendations REFC

System Design Checklist R 168 Intel® 815 Chipset Platform Design Guide 13.9 LAN Checklist Checklist Items Recommendations TDP, TDN, RDP, RDN •

System Design Checklist R Intel® 815 Chipset Platform Design Guide 169 13.10.1 Power Checklist Items Recommendations V_CPU_IO[1:0] • The po

Introduction R Intel® 815 Chipset Platform Design Guide 17 elimination of ISA provides true plug-and-play for the platform. Traditionally, the

System Design Checklist R 170 Intel® 815 Chipset Platform Design Guide This page is intentionally left blank.

Third-Party Vendor Information R Intel® 815 Chipset Platform Design Guide 171 14 Third-Party Vendor Information This design guide has been co

Third-Party Vendor Information R 172 Intel® 815 Chipset Platform Design Guide TMDS Transmitters • Silicon Images John Nelson (408) 873-3111 •

Appendix A: Customer Reference Board (CRB) R Intel® 815 Chipset Platform Design Guide 173 Appendix A: Customer Reference Board (CRB) This sect

5544332211D DC CB BA AIntel(R) Pentium(R) III Processor (CPUID = 068xh), Intel(R) Celeron(TM) Processor (CPUID= 068xh), and Future 0.13 Micron Socket

5544332211D DC CB BA AVRMCTRLADDRDATAADDRCLOCKDATACTRLUSBIDE PrimaryIDE Secondary370-PIN SOCKET PROCESSORGMCHICHModulesAGPConnectorDigital VideoOut De

5544332211D DC CB BA A370PGA SOCKET, PART 1INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD370-PIN SOCKET, PART 1401.03-26-013Platform Apps Engineering

5544332211D DC CB BA A330Do Not Stuff C10Place within 0.5"of clock pin (W37)ITP Test Port OptionClock Frequency Selection370PGA SOCKET, PART 2Deb

5544332211D DC CB BA AClock SynthesizerNotes:Place all decoupling caps as close to VCC/GND pins as possiblePCI_0/ICH pin must go to ICH.This clock can

5544332211D DC CB BA A82815B GMCH, PART 1, 4, AND 5HOST INTERFACE, POWER & GNDNOTE: VCC1_8 IS A NOMINAL 1.85VDO NOT STUFF C122PLACE SITE W/IN 0.5&

Introduction R 18 Intel® 815 Chipset Platform Design Guide 1.3.2 Component Features Figure 2. GMCH Block Diagram System bus (66/100/133 MHz) Pro

5544332211D DC CB BA APlace HUBREFgeneration circuit inthe middle of GMCHand ICH.Host freq; high = 100, low = 66FSB PMOS kickerHost freq; high = 133,

5544332211D DC CB BA APlace resistor as close aspossible to GMCH.Place resistoras close aspossible toGMCH andvia straight toplane.Do not stuff C196Pla

5544332211D DC CB BA AAGP CONNECTORINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDAGP CONNECTOR401.03-26-019Platform Apps Engineering1900 Prairie City

5544332211D DC CB BA ADIMM0SLAVE ADDRESS = 1010000BSystem Memory DIMM0SYSTEM MEMORYINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDSYSTEM MEMORY: DIMM0

5544332211D DC CB BA ASystem Memory: DIMM1DIMM1SLAVE ADDRESS = 1010001BSYSTEM MEMORYINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDSYSTEM MEMORY: DIMM

5544332211D DC CB BA APlace R178as close aspossible toICHPlace C291as close aspossible toICHDon't Stuff R173For Test/DebugNo PopICH, PART 1INTEL(

5544332211D DC CB BA AICH, PART 2SocketedMinimize StubLength toJumpersR85 and R203 forTest/DebugDebug OnlyEmptyNote: Depending on the versionof ICH b

5544332211D DC CB BA ARP68 for Test/DebugDistribute close to each power pin40 PIN_TSOP_SKTFIRMWARE HUB (FWH) SOCKETNOTE: This is a TSOP Implementation

5544332211D DC CB BA APlace nearVREF pinTest/Debug HeaderUnused GPIOsDecouplingPlace 10.1UF capnear eachpower pinPulldown on SYSOPT for IO address of

5544332211D DC CB BA APCI CONNECTOR 0(DEV Ah)INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDPCI CONNECTOR 0401.03-26-0116Platform Apps Engineering1900

Introduction R Intel® 815 Chipset Platform Design Guide 19 • Accelerated Graphics Port (AGP) Interface  Supports AGP 2.0, including 4X AGP

5544332211D DC CB BA AFor Debug OnlyFor Debug OnlyFor Debug OnlyFor Debug OnlyDo Not Stuff R192PCI CONNECTOR 1(DEV Bh)INTEL(R) 82815 CHIPSET CUSTOMER

5544332211D DC CB BA AIDE CONNECTORSINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDULTRA DMA/66 CONNECTOR401.03-26-0118Platform Apps Engineering1900 P

5544332211D DC CB BA ADo Not StuffDo Not StuffPOLYSWITCH_RUSB250NO POPNPO NPOUSB HUBINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDUSB HUB401.03-26-01

5544332211D DC CB BA APARALLEL PORTINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDPARALLEL PORT401.03-26-0120Platform Apps Engineering1900 Prairie Cit

5544332211D DC CB BA APLACE CLOSE TO HEADERPLACE CLOSE TO HEADER2ND COM Header OptionNOTE: If Wake from S3 onSerial Modem is not supporteddo not stuff

5544332211D DC CB BA AKeyboard/Mouse PortFloppy Disk HeaderINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDKEYBOARD/MOUSE/FLOPPY401.03-26-0122Platform

5544332211D DC CB BA A25V25V25V25V10% 10%10% 10%50V 50V 50V 50VThe game port capacitors together and to SIO AVSS.Tie to system ground at only a single

5544332211D DC CB BA APlace this capacitor near pin 40.Digital Video Out Connector(FOR DEBUG PURPOSES ONLY)INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE B

5544332211D DC CB BA ADo Not Populate5V to 3.3V TRANSLATION/ISOLATIONDO NOT STUFF C100 and C102DO NOT STUFF C119 and C122Place R66, R67, & R69 clo

5544332211D DC CB BA AAudio/Modem RiserINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDAUDIO/MODEM RISER401.03-26-0126Platform Apps Engineering1900 Pra

R 2 Intel® 815 Chipset Platform Design Guide Information in this document is provided in connection with Intel® products. No lic

Introduction R 20 Intel® 815 Chipset Platform Design Guide 1.3.2.2 Intel® 82801AA I/O Controller Hub (ICH) The I/O Controller Hub provides the I/

5544332211D DC CB BA AMC78M05CDTAC'97 Audio CodecINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDAC'97 AUDIO CODEC401.03-26-0127Platform Apps

5544332211D DC CB BA ASTEREO HP/SPEAKER OUTMICROPHONE INPUTLINE_IN ANALOG INPUTCD ANALOG INPUTAudio ConnectorsINTEL(R) 82815 CHIPSET CUSTOMER REFERENC

5544332211D DC CB BA ADO NOT STUFFLAN DecouplingDistribute around PowerPins Close to 82559.Place C305/C306Close to Ball A10LANINTEL(R) 82815 CHIPSET C

5544332211D DC CB BA ADO NOT STUFF R198NOTE: This circuit is for debug purpose only.NOTE: Chassis Ground, useplane for this signalNO POP R295Place R29

5544332211D DC CB BA ASN74LVC07A HAS 5V INPUT AND OUTPUT TOLERANCEDO NOT POPULATEDO NOT POPULATEPLACE C99 AT THE REGULATORLT1587-ADJLT1587ADJLT1117-3_

5544332211D DC CB BA ANO STUFF R210Route VR6 GND to VDDQ output caps and then via to ground.AGP, VCMOS Voltage RegulatorINTEL(R) 82815 CHIPSET CUSTOME

5544332211D DC CB BA ARefer to VR Supplier for Layout GuidelinesProcessor Voltage RegulatorStuff only oneINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOA

5544332211D DC CB BA AINFRAREDPOWER SW.H.D. LEDPOWER LEDKEY LOCKSPEAKERFAN HEADERSOn-Board LED indicates th StandbyWell is on to prevent Hot-SwappingM

5544332211D DC CB BA ASN74LVC06A has 5Vinput toleranceITP RESET CIRCUIT - FOR DEBUG ONLYDO NOT POPULATE R95RESUME RESET CIRCUITRYSchmitt Trigger Logic

5544332211D DC CB BA AUnused GatesPCI BusICHCPUFor Future Compatability UpgradeINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDPULLUP/PULLDOWN RESISTOR

Introduction R Intel® 815 Chipset Platform Design Guide 21 1.3.3 Platform Initiatives 1.3.3.1 Universal Socket 370 Design The Intel 815 chips

5544332211D DC CB BA AVTT DECOUPLING0603 Package placed within 200mils of VTT Termination R-packs.One Capacitor for every 2 R-packsVCCVID DECOUPLINGPl

5544332211D DC CB BA AGMCH DECOUPLING DISPLAY CACHE DECOUPLING ICH DECOUPLINGSYSTEM MEMORY DECOUPLINGBULK POWER DECOUPLING3 VOLT DECOUPLINGGMCH Core P

5544332211D DC CB BA APROBE_CONNECTORHub Interface ConnectorINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDHUB INTERFACE CONNECTOR401.03-26-0139Platfo

5544332211D DC CB BA AINTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARDTHERMTRIP401.03-26-0140Platform Apps Engineering1900 Prairie City RoadFolsom, CA

Introduction R 22 Intel® 815 Chipset Platform Design Guide 1.3.3.6 Manageability The Intel 815 chipset platform integrates several functions desi

Introduction R Intel® 815 Chipset Platform Design Guide 23 1.3.3.7 AC’97 The Audio Codec ’97 (AC’97) specification defines a digital interface

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General Design Considerations R Intel® 815 Chipset Platform Design Guide 25 2 General Design Considerations This document provides motherboar

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Component Quadrant Layouts R Intel® 815 Chipset Platform Design Guide 27 3 Component Quadrant Layouts Figure 4 illustrates the relative signa

Component Quadrant Layouts R 28 Intel® 815 Chipset Platform Design Guide Figure 5 illustrates the relative signal quadrant locations on the ICH b

Universal Socket 370 Design R Intel® 815 Chipset Platform Design Guide 29 4 Universal Socket 370 Design 4.1 Universal Socket 370 Definitions

R Intel® 815 Chipset Platform Design Guide 3 Contents 1 Introduction ...

Universal Socket 370 Design R 30 Intel® 815 Chipset Platform Design Guide Signal Name or Pin Number Function In Intel® Pentium® III Processor (C

Universal Socket 370 Design R Intel® 815 Chipset Platform Design Guide 31 Table 4. Clock Synthesizer Considerations for Universal Socket 370 D

Universal Socket 370 Design R 32 Intel® 815 Chipset Platform Design Guide 4.2.2 Identifying the Processor at the Socket For the platform to conf

Universal Socket 370 Design R Intel® 815 Chipset Platform Design Guide 33 4.2.3 Setting the Appropriate Processor VTT Level Because the Penti

Universal Socket 370 Design R 34 Intel® 815 Chipset Platform Design Guide 4.2.4 VTT Processor Pin AG1 Processor pin AG1 requires additional atte

Universal Socket 370 Design R Intel® 815 Chipset Platform Design Guide 35 Figure 11. Processor Identification Strap on GMCH 10 KΩTUAL5SMAA[12]

Universal Socket 370 Design R 36 Intel® 815 Chipset Platform Design Guide 4.2.6 Configuring Non-VTT Processor Pins When asserted, the VTTPWGRD s

Universal Socket 370 Design R Intel® 815 Chipset Platform Design Guide 37 4.2.7 VCMOS Reference In previous platforms supporting the Pentium I

Universal Socket 370 Design R 38 Intel® 815 Chipset Platform Design Guide 4.2.8 Processor Signal PWRGOOD The processor signal PWRGOOD is specifi

Universal Socket 370 Design R Intel® 815 Chipset Platform Design Guide 39 4.2.9 APIC Clock Voltage Switching Requirements The processor’s API

R 4 Intel® 815 Chipset Platform Design Guide 5.2 General Topology and Layout Guidelines...

Universal Socket 370 Design R 40 Intel® 815 Chipset Platform Design Guide 4.2.10 GTLREF Topology and Layout In a platform supporting the future

Universal Socket 370 Design R Intel® 815 Chipset Platform Design Guide 41 4.3 Power Sequencing on Wake Events In addition to the mechanism fo

Universal Socket 370 Design R 42 Intel® 815 Chipset Platform Design Guide 4.3.2 Gating of PWROK to ICH With power being gated to the Intel CK-8

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 43 5 System Bus Design Guidelines The Pentium III processor delivers

System Bus Design Guidelines R 44 Intel® 815 Chipset Platform Design Guide Table 6. Intel® Pentium® III Processor AGTL/AGTL+ Parameters for Examp

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 45 Table 7. Example TFLT_MAX Calculations for 133 MHz Bus 1 Driver Rec

System Bus Design Guidelines R 46 Intel® 815 Chipset Platform Design Guide 5.2 General Topology and Layout Guidelines Figure 19. Topology for

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 47 5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals Ground Refer

System Bus Design Guidelines R 48 Intel® 815 Chipset Platform Design Guide Minimizing Cross-Talk The following general rules minimize the impact

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 49 5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals

R Intel® 815 Chipset Platform Design Guide 5 7.3.2.2 AGP-Only Motherboard Guidelines...86 7.3.3 AGP Rout

System Bus Design Guidelines R 50 Intel® 815 Chipset Platform Design Guide 5.2.1.2 THRMDP and THRMDN These traces (THRMDP and THRMDN) route the

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 51 5.3 Electrical Differences for Universal PGA370 Designs There are

System Bus Design Guidelines R 52 Intel® 815 Chipset Platform Design Guide 5.4 PGA370 Socket Definition Details The following table compares the

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 53 Pin # Pin Name Intel® Celeron™ Processor (CPUID=068xh) Pin Name

System Bus Design Guidelines R 54 Intel® 815 Chipset Platform Design Guide Pin # Pin Name Intel® Celeron™ Processor (CPUID=068xh) Pin Name Int

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 55 Pin # Pin Name Intel® Celeron™ Processor (CPUID=068xh) Pin Name

System Bus Design Guidelines R 56 Intel® 815 Chipset Platform Design Guide 5.5 BSEL[1:0] Implementation Differences A future 0.13 micron socket

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 57 5.6 CLKREF Circuit Implementation The CLKREF input (used by the Pe

System Bus Design Guidelines R 58 Intel® 815 Chipset Platform Design Guide 5.8 Processor Reset Requirements Universal PGA370 designs must route

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 59 5.9 Processor PLL Filter Recommendations Intel PGA370 processors h

R 6 Intel® 815 Chipset Platform Design Guide 10.2.5 Layout for Both Host-Side and Device-Side Cable Detection ...118 10.3 AC’97 ...

System Bus Design Guidelines R 60 Intel® 815 Chipset Platform Design Guide Figure 26. Filter Specification 0dB-28dB-34dB0.2dB-0.5 dB1 MHz 66 MHz

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 61 5.9.3 Recommendation for Intel Platforms The following tables cont

System Bus Design Guidelines R 62 Intel® 815 Chipset Platform Design Guide Figure 27. Example PLL Filter Using a Discrete Resistor ProcessorPLL1P

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 63 5.9.4 Custom Solutions As long as designers satisfy filter performa

System Bus Design Guidelines R 64 Intel® 815 Chipset Platform Design Guide Figure 30. Capacitor Placement on the Motherboard 5.11.2 VTT Decoupl

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 65 5.12 Thermal Considerations 5.12.1 Heatsink Volumetric Keepout Reg

System Bus Design Guidelines R 66 Intel® 815 Chipset Platform Design Guide Figure 31. Heatsink Volumetric Keepout Regions Figure 32. Motherboard

System Bus Design Guidelines R Intel® 815 Chipset Platform Design Guide 67 5.13 Debug Port Changes Due to the lower voltage technology employ

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System Memory Design Guidelines R Intel® 815 Chipset Platform Design Guide 69 6 System Memory Design Guidelines 6.1 System Memory Routing Gu

R Intel® 815 Chipset Platform Design Guide 7 13.3.1 AGP Interface 1X Mode Checklist...15

System Memory Design Guidelines R 70 Intel® 815 Chipset Platform Design Guide 6.2 System Memory 2-DIMM Design Guidelines 6.2.1 System Memory 2-

System Memory Design Guidelines R Intel® 815 Chipset Platform Design Guide 71 6.2.2 System Memory 2-DIMM Layout Guidelines Figure 36. System

System Memory Design Guidelines R 72 Intel® 815 Chipset Platform Design Guide Figure 37. System Memory Routing Example sys_mem_routing_ex NOTE:

System Memory Design Guidelines R Intel® 815 Chipset Platform Design Guide 73 6.3 System Memory 3-DIMM Design Guidelines 6.3.1 System Memory

System Memory Design Guidelines R 74 Intel® 815 Chipset Platform Design Guide 6.3.2 System Memory 3-DIMM Layout Guidelines Figure 39. System Mem

System Memory Design Guidelines R Intel® 815 Chipset Platform Design Guide 75 6.4 System Memory Decoupling Guidelines A minimum of eight 0.1

System Memory Design Guidelines R 76 Intel® 815 Chipset Platform Design Guide Figure 40. Intel® 815 Chipset Platform Decoupling Example Yellow l

System Memory Design Guidelines R Intel® 815 Chipset Platform Design Guide 77 Figure 41. Intel® 815 Chipset Platform Decoupling Example 6.5

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AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 79 7 AGP/Display Cache Design Guidelines For the detailed AGP

R 8 Intel® 815 Chipset Platform Design Guide Figures Figure 1. System Block Diagram ...

AGP/Display Cache Design Guidelines R 80 Intel® 815 Chipset Platform Design Guide 7.1.1 Graphics Performance Accelerator (GPA) The GMCH multiple

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 81 Figure 42. AGP Left-Handed Retention Mechanism Figure 43.

AGP/Display Cache Design Guidelines R 82 Intel® 815 Chipset Platform Design Guide ECR #48 can be viewed on the Intel Web site at: http://develop

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 83 7.2.1 AGP Interface Signal Groups The signals on the AGP in

AGP/Display Cache Design Guidelines R 84 Intel® 815 Chipset Platform Design Guide 7.3 Standard AGP Routing Guidelines These routing guidelines c

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 85 separately. The maximum length allowed for the AGP interface

AGP/Display Cache Design Guidelines R 86 Intel® 815 Chipset Platform Design Guide 7.3.2.2 AGP-Only Motherboard Guidelines For motherboards that

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 87 between them. This pair should be separated from the rest of

AGP/Display Cache Design Guidelines R 88 Intel® 815 Chipset Platform Design Guide 7.3.4 AGP Clock Routing The maximum total AGP clock skew, betw

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 89 Figure 45. AGP Decoupling Capacitor Placement Example AGP_de

R Intel® 815 Chipset Platform Design Guide 9 Figure 49. Schematic of RAMDAC Video Interface...

AGP/Display Cache Design Guidelines R 90 Intel® 815 Chipset Platform Design Guide 7.4 AGP Down Routing Guidelines These routing guidelines cover

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 91 Figure 1. AGP Down 2X/4X Routing Recommendations AGP_Down_1

AGP/Display Cache Design Guidelines R 92 Intel® 815 Chipset Platform Design Guide 7.4.4 AGP Clock Routing The maximum total AGP clock skew, betw

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 93 7.5 AGP 2.0 Power Delivery Guidelines 7.5.1 VDDQ Generatio

AGP/Display Cache Design Guidelines R 94 Intel® 815 Chipset Platform Design Guide Figure 46. AGP VDDQ Generation Example Circuit SHDN

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 95 7.5.2 VREF Generation for AGP 2.0 (2X and 4X) VREF generati

AGP/Display Cache Design Guidelines R 96 Intel® 815 Chipset Platform Design Guide Figure 47. AGP 2.0 VREF Generation and Distribution C8500 pFAGP

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 97 7.6 Additional AGP Design Guidelines 7.6.1 Compensation The

AGP/Display Cache Design Guidelines R 98 Intel® 815 Chipset Platform Design Guide The pull-up/pull-down resistor value requirements are Rmin = 4

AGP/Display Cache Design Guidelines R Intel® 815 Chipset Platform Design Guide 99 7.8 AGP / Display Cache Shared Interface As described earli