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Intel® Solid-State Drive 730 Series

December 2014 Product Specification

330177-003 15

4.2.2 Power Pin Signal Definitions

Table 10: Serial ATA Power Pin Definitions

Name

Definition

Mating Order

3.3V Power; not used

2nd Mate

3.3V Power; not used

2nd Mate

3.3V Power; not used

2nd Mate

3,4

Ground

1st Mate

Ground

1st Mate

Ground

1st Mate

3,5

5V Power

1st Mate

3,5

5V Power

2nd Mate

3,5

5V Power

2nd Mate

P10

Ground

1st Mate

P11

DAS

Device Activity Signal

2nd Mate

P12

3, 4

Ground

1st Mate

P13

12V Power

1st Mate

P14

12V Power

2nd Mate

P15

12V Power

2nd Mate

Notes:

1. All pins are in a single row, with a 1.27 mm (0.050-inch) pitch.

2. Pins P1, P2 and P3 are connected together; Pins P13, P14 and P15 are connected together. Although they are not

connected internally to the device, the host may apply voltage on these pins.

3. The mating sequence is:

• Ground pins P4-P6, P10, P12 and the 5V power pin P7

• Signal pins and the rest of the 5V power pins P8-P9

4. Ground connectors P4 and P12 may contact before the other 1st mate pins in both the power and signal connectors to

discharge ESD in a suitably configured backplane connector.

5. Power pins P7, P8, and P9 are internally connected to one another within the device.

6. The host may ground P11 if it is not used for Device Activity Signal (DAS).

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 26 27

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