Intel i7-2960XM Arkusz Danych Strona 60
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Register Description
60 Datasheet
2.10.2 MC_CHANNEL_0_DIMM_INIT_CMD
MC_CHANNEL_1_DIMM_INIT_CMD
MC_CHANNEL_2_DIMM_INIT_CMD
Integrated Memory Controller DIMM initialization command register. This register is
used to sequence the channel through the physical layer training required for DDR.
Device: 4, 5, 6
Function: 0
Offset: 54h
Access as a Dword
Bit Type
Reset
Value
Description
17 WO 0
ASSERT_CKE.
When set, all CKE will be asserted. Write a 0 to this bit to stop the init block
from driving CKE. This bit has no effect once MC_CONTROL.INIT_DONE is set.
This bit must be used during INITIALIZATION only and be cleared out before
MC_CONTROL.INIT_DONE is set. This bit must not be asserted during
initialization for S3 resume.
16 RW 0
DO_RCOMP.
When set, an RCOMP will be issued to the rank specified in the RANK field.
15 RW 0
DO_ZQCL.
When set, a ZQCL will be issued to the rank specified in the RANK field.
14 RW 0
WRDQDQS_MASK.
When set, the Write DQ-DQS training will be skipped.
13 RW 0
WRLEVEL_MASK.
When set, the Write Levelization step will be skipped.
12 RW 0
RDDQDQS_MASK.
When set, the Read DQ-DQS step will be skipped.
11 RW 0
RCVEN_MASK.
When set, the RCVEN step will be skipped.
10 WO 0
RESET_FIFOS.
When set, the TX and RX FIFO pointers will be reset at the next BCLK edge. The
Bubble Generators will also be reset.
9RW0
IGNORE_RX.
When set, the read return datapath will ignore all data coming from the RX
FIFOS. This is done by gating the early valid bit.
8RW0
STOP_ON_FAIL.
When set along with the AUTORESETDIS not being set, the phyinit FSM will stop
if a step has not completed after timing out.
7:5 RW 0
RANK.
The rank currently being tested. The PhyInit FSM must be sequenced for every
rank present in the channel. The rank value is set to the rank being trained.
4:2 RW 0
NXT_PHYINIT_STATE.
Set to sequence the physical layer state machine.
000 = IDLE
001 = RD DQ-DQS
010 = RcvEn Bitlock
011 = Write Level
100 = WR DQ-DQS.
1RW0
AUTODIS.
Disables the automatic training where each step is automatically incremented.
When set, the physical layer state machine must be sequenced with software.
The training FSM must be sequenced using the NXT_PHYINIT_STATE field.
0WO0
TRAIN.
Cycle through the training sequence for the rank specified in the RANK field.
- Datasheet, Volume 2 1
- Contents 3
- 4 Datasheet 4
- Datasheet 5 5
- 6 Datasheet 6
- Datasheet 7 7
- 8 Datasheet 8
- Revision History 9
- 10 Datasheet 10
- 1 Introduction 11
- Introduction 12
- 12 Datasheet 12
- 1.2 References 13
- 14 Datasheet 14
- 2 Register Description 15
- 2.3 Device Mapping 17
- Control Registers 24
- Address Registers 25
- Rank Registers 26
- Thermal Control Registers 27
- 2.5 PCI Standard Registers 36
- Identification Register 38
- Express space 39
- 2.6.1 SAD_PAM0123 41
- 2.6.2 SAD_PAM456 43
- 2.6.3 SAD_HEN 44
- 2.6.4 SAD_SMRAM 44
- 2.6.5 SAD_PCIEXBAR 45
- 19:6 RW 46
- 2:1 RW 46
- 2.7 Intel QPI Link Registers 47
- 2.8.2 MC_STATUS 49
- 13:12 RW0C 50
- 11:0 RW0C 50
- 2.8.4 MC_SMI_SPARE_CNTRL 51
- 2.8.5 MC_RESET_CONTROL 51
- 2.8.6 MC_CHANNEL_MAPPER 52
- 2.8.7 MC_MAX_DOD 53
- 2.8.8 MC_RD_CRDT_INIT 54
- 2.8.9 MC_CRDT_WR_THLD 55
- 2.8.10 MC_SCRUBADDR_LO 55
- 2.8.11 MC_SCRUBADDR_HI 56
- 29:28 RW 58
- 25:24 RW 58
- 21:20 RW 58
- 17:16 RW 58
- 13:12 RW 58
- Registers 59
- MC_CHANNEL_1_DIMM_INIT_CMD 60
- MC_CHANNEL_2_DIMM_INIT_CMD 60
- MC_CHANNEL_1_DIMM_INIT_PARAMS 61
- MC_CHANNEL_2_DIMM_INIT_PARAMS 61
- MC_CHANNEL_1_DIMM_INIT_STATUS 62
- MC_CHANNEL_2_DIMM_INIT_STATUS 62
- 2.10.5 MC_CHANNEL_0_DDR3CMD 63
- MC_CHANNEL_1_DDR3CMD 63
- MC_CHANNEL_2_DDR3CMD 63
- 3:2 RW 0 64
- 31:16 RW 0 64
- 15:0 RW 0 64
- 23:20 RW 0 65
- 19:16 RW 0 65
- 7:0 RW 0 65
- MC_CHANNEL_1_RANK_TIMING_A 66
- MC_CHANNEL_2_RANK_TIMING_A 66
- 18:15 RW 0 67
- 14:11 RW 0 67
- 10:7 RW 0 67
- 6:4 RW 0 68
- 3:1 RW 0 68
- MC_CHANNEL_1_RANK_TIMING_B 69
- MC_CHANNEL_2_RANK_TIMING_B 69
- 29:19 RW 0 70
- 18:9 RW 0 70
- 8:0 RW 0 70
- MC_CHANNEL_1_WAQ_PARAMS 75
- MC_CHANNEL_2_WAQ_PARAMS 75
- MC_CHANNEL_1_ADDR_MATCH 81
- MC_CHANNEL_2_ADDR_MATCH 81
- 31:0 RW 0 82
- 2:1 RW 0 82
- Datasheet 83 83
- Register Description 83
- 26:24 RW 0 87
- 23:0 RW 0 87
- 13:4 RW 0 90
- 3:0 RW 0 90
- 2.13 Memory Thermal Control 92
- Throttling (CLTT) 93
- 2.14.2 MC_DIMM_CLK_RATIO 98
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