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Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage
700 MHz, Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
283653-002 Datasheet 71
appropriate pins/balls on both agents on the system bus if they are used. During power-on
configuration, DEP[7:0]# signals can be enabled for ECC checking or disabled for no checking.
DRDY# (I/O - GTL+)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating
valid data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle
clocks. This signal must be connected to the appropriate pins/balls on both agents on the system
bus.
EDGCTRLP (Analog)
The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the GTL+ output
buffers. Connect the signal to V
SS
with a 110-Ω, 1% resistor.
FERR# (O - 1.5V Tolerant Open-drain)
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked
floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and it
is included for compatibility with systems using DOS-type floating-point error reporting.
FLUSH# (I - 1.5V Tolerant)
When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache
lines in the Modified state and invalidates all internal cache lines. At the completion of a flush
operation, the processor issues a Flush Acknowledge transaction. The processor stops caching any
new data while the FLUSH# signal remains asserted.
On the active-to-inactive transition of RESET#, each processor bus agent samples FLUSH# to
determine its power-on configuration.
GHI# (I - 1.5V Tolerant)
The GHI# signal controls which operating mode bus ratio is selected in a mobile Pentium III
processor featuring Intel SpeedStep technology. On the processor featuring Intel SpeedStep
technology, this signal is latched when BCLK restarts in Deep Sleep state and determines which
of two bus ratios is selected for operation. This signal is ignored when the processor is not in the
Deep Sleep state. This signal is a “Don’t Care” on processors that do not feature Intel SpeedStep
technology. This signal has an on-die pull-up to V
CCT
and should be driven with an Open-drain
driver with no external pull-up.
HIT# (I/O - GTL+), HITM# (I/O - GTL+)
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation
results, and must be connected to the appropriate pins/balls on both agents on the system bus.
- Mobile Intel 1
- Pentium 1
- Processor in BGA2 and Micro 1
- PGA2 Packages 1
- Contents 4
- Figures 6
- Revision History 8
- Table 33 9
- 1. Introduction 10
- V0000-03 11
- V0000-04 12
- 1.1 Overview 13
- 1.2 Terminology 13
- 1.3 References 14
- Features 15
- 2.2 Power Management 16
- 2.2.4 Stop Grant State 17
- 2.2.5 Quick Start State 18
- 2.2.7 Sleep State 18
- 2.2.8 Deep Sleep State 19
- 2.3 GTL+ Signals 20
- EAX[31:0] EBX[7:0] 21
- X 0 6 8 X 02 21
- 3. Electrical Specifications 22
- 3.1.4 Unused Signals 24
- 3.1.5.3 Other Signals 25
- 3.2.2 Voltage Planes 26
- 3.5 Maximum Ratings 27
- 3.6 DC Specifications 28
- 3.7 AC Specifications 32
- IL25,max 34
- IH25,min 34
- D0003-02 38
- D0005-00 39
- D0007-01 40
- D0008-01 41
- D0009-01 42
- V0036-00 43
- Quality Specifications 44
- V0014-02 46
- Time dependant 47
- 5. Mechanical Specifications 49
- 5.3 Signal Listings 54
- VCC Other VCCT VSS 55
- Decoupling 55
- 6. Thermal Specifications 63
- 0.6 / 0.5 64
- 35 °C 64
- 6.1 Thermal Diode 65
- Configuration 66
- 8. Processor Interface 67
- AP[1:0]# (I/O - GTL+) 68
- BCLK (I - 2.5V Tolerant) 68
- BERR# (I/O - GTL+) 68
- BINIT# (I/O - GTL+) 68
- 00 66 MHz 70
- 01 100 MHz 70
- 10 Reserved 70
- 11 133 MHz 70
- IGNNE# (I - 1.5V Tolerant) 72
- INIT# (I - 1.5V Tolerant) 72
- INTR (I - 1.5V Tolerant) 72
- D0026-01 74
- RP# (I/O - GTL+) 75
- RS[2:0]# (I - GTL+) 75
- RSP# (I - GTL+) 75
- RSVD (TBD) 75
- VREF (Analog) 79
- 8.2 Signal Summaries 80
- A.1 Introduction 82
- A.2 Filter Specification 82
- A.4 Comments 85
- Processor 86
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