Intel LE80535VC600512 Arkusz Danych Pobierz pdf (Strona 75)

Mobile Intel

Celeron

Processor (0.18µ) in BGA2 and Micro-PGA2 Packages

283654-003 Datasheet 75

8.2 Signal Summaries

Table 37 through Table 40 list the attributes of the processor input, output, and I/O signals.

Table 37. Input Signals

Name Active Level Clock Signal Group Qualified

A20M# Low Asynch CMOS Always

BCLK High — System Bus Always

BPRI# Low BCLK System Bus Always

BSEL[1:0] High Asynch Implementation Always

DEFER# Low BCLK System Bus Always

FLUSH# Low Asynch CMOS Always

IGNNE# Low Asynch CMOS Always

INIT# Low Asynch System Bus Always

INTR High Asynch CMOS APIC disabled

mode

LINT[1:0] High Asynch APIC APIC enabled

mode

NMI High Asynch CMOS APIC disabled

mode

PICCLK High — APIC Always

PREQ# Low Asynch Implementation Always

PWRGOOD High Asynch Implementation Always

RESET# Low BCLK System Bus Always

RS[2:0]# Low BCLK System Bus Always

RSP# Low BCLK System Bus Always

SLP# Low Asynch Implementation Stop Grant state

SMI# Low Asynch CMOS Always

STPCLK# Low Asynch Implementation Always

TCK High — JTAG

TDI TCK JTAG

TMS TCK JTAG

TRDY# Low BCLK System Bus Response phase

TRST# Low Asynch JTAG

1 2 ... 70 71 72 73 74 75 76 77 78 79 80

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Intel LE80535VC600512 Arkusz Danych Strona 75