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Datasheet, Volume 1 51

Power Management

Entry and exit of the C-States at the thread and core level are shown in Figure 4-3.

While individual threads can request low power C-states, power saving actions only

take place once the core C-state is resolved. Core C-states are automatically resolved

by the processor. For thread and core C-states, a transition to and from C0 is required

before entering any other C-state.

Note: If enabled, the core C-state will be C1E if all enabled cores have also resolved a core C1 state or higher.

Figure 4-2. Idle Power Management Breakdown of the Processor Cores

Processor Package State

Core 1 State

Thread 1Thread 0

Core 0 State

Thread 1Thread 0

Figure 4-3. Thread and Core C-State Entry and Exit

C1 C1E C6C3

MWAIT(C1), HLT

MWAIT(C6),

P_LVL3 I/O Read

MWAIT(C3),

P_LV2 I/O Read

MWAIT(C1), HLT

(C1E Enabled)

Table 4-8. Coordination of Thread Power States at the Core Level

Processor Core

C-State

Thread 1

C0 C1 C3 C6

Thread 0

C0 C0 C0 C0 C0

C1 C0 C1

C3 C0 C1

C3 C3

C6 C0 C1

C3 C6

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 111 112

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Intel CM8063701450500 Arkusz Danych Strona 51