Intel CM8063701219000 Arkusz Danych Strona 1

Document Number: 324642-0032nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, andIntel® Celeron® Processo

10 Datasheet, Volume 2Revision History§ §Revision NumberDescriptionRevision Date001 • Initial releaseJanuary 2011002•Added Intel® Pentium® processor f

Processor Configuration Registers100 Datasheet, Volume 22.6.20 PMLIMITU1—Prefetchable Memory Limit Address Upper RegisterThe functionality associated

Datasheet, Volume 2 101Processor Configuration Registers2.6.22 INTRLINE1—Interrupt Line RegisterThis register contains interrupt line routing informat

Processor Configuration Registers102 Datasheet, Volume 22.6.24 BCTRL1—Bridge Control RegisterThis register provides extensions to the PCICMD register

Datasheet, Volume 2 103Processor Configuration Registers1 RW 0b UncoreSERR Enable (SERREN)0 = No forwarding of error messages from secondary side to p

Processor Configuration Registers104 Datasheet, Volume 22.6.25 PM_CAPID1—Power Management Capabilities RegisterB/D/F/Type: 0/1/0–2/PCIAddress Offset:

Datasheet, Volume 2 105Processor Configuration Registers2.6.26 PM_CS1—Power Management Control/Status RegisterB/D/F/Type: 0/1/0–2/PCIAddress Offset: 8

Processor Configuration Registers106 Datasheet, Volume 22.6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities RegisterThis capability is used to uni

Datasheet, Volume 2 107Processor Configuration Registers2.6.28 SS—Subsystem ID and Subsystem Vendor ID RegisterSystem BIOS can be used as the mechanis

Processor Configuration Registers108 Datasheet, Volume 22.6.30 MC—Message Control RegisterSystem software can modify bits in this register, but the de

Datasheet, Volume 2 109Processor Configuration Registers2.6.31 MA—Message Address Register2.6.32 MD—Message Data Register2.6.33 PEG_CAPL—PCI Express-G

Datasheet, Volume 2 11Introduction1 IntroductionThis is Volume 2 of the Datasheet for the following products: • 2nd Generation Intel® Core™ processor

Processor Configuration Registers110 Datasheet, Volume 22.6.34 PEG_CAP—PCI Express-G Capabilities RegisterThis register indicates PCI Express device c

Datasheet, Volume 2 111Processor Configuration Registers2.6.36 DCTL—Device Control RegisterThis register provides control for PCI Express device speci

Processor Configuration Registers112 Datasheet, Volume 22.6.37 DSTS—Device Status RegisterReflects status corresponding to controls in the Device Cont

Datasheet, Volume 2 113Processor Configuration Registers2.6.38 LCTL—Link Control RegisterThis register allows control of PCI Express link.B/D/F/Type:

Processor Configuration Registers114 Datasheet, Volume 26RW 0bUncoreCommon Clock Configuration (CCC)0 = Indicates that this component and the componen

Datasheet, Volume 2 115Processor Configuration Registers2.6.39 LSTS—Link Status RegisterThis register indicates PCI Express link status.B/D/F/Type: 0/

Processor Configuration Registers116 Datasheet, Volume 22.6.40 SLOTCAP—Slot Capabilities RegisterPCI Express Slot related registers allow for the supp

Datasheet, Volume 2 117Processor Configuration Registers16:15 RW-O 00b UncoreSlot Power Limit Scale (SPLS)This field specifies the scale used for the

Processor Configuration Registers118 Datasheet, Volume 22.6.41 SLOTCTL—Slot Control RegisterPCI Express Slot related registers allow for the support o

Datasheet, Volume 2 119Processor Configuration Registers7:6 RO 00b UncoreReserved for Attention Indicator Control (AIC)If an Attention Indicator is im

Introduction12 Datasheet, Volume 2

Processor Configuration Registers120 Datasheet, Volume 22.6.42 SLOTSTS—Slot Status RegisterThis is for PCI Express Slot related registers.B/D/F/Type:

Datasheet, Volume 2 121Processor Configuration Registers3 RW1C 0b UncorePresence Detect Changed (PDC)A pulse indication that the inband presence detec

Processor Configuration Registers122 Datasheet, Volume 22.6.43 RCTL—Root Control RegisterThis register allows control of PCI Express Root Complex spec

Datasheet, Volume 2 123Processor Configuration Registers2.6.44 LCTL2—Link Control 2 RegisterB/D/F/Type: 0/1/0–2/PCIAddress Offset: D0–D1hReset Value:

Processor Configuration Registers124 Datasheet, Volume 26RWS 0bPowergoodSelectable De-emphasis (selectabledeemphasis)When the Link is operating at 5GT

Datasheet, Volume 2 125Processor Configuration Registers2.7 PCI Device 1, Function 0–2 Extended Configuration RegistersTable 2-9 lists the registers a

Processor Configuration Registers126 Datasheet, Volume 22.7.2 PVCCAP2—Port VC Capability Register 2This register describes the configuration of PCI Ex

Datasheet, Volume 2 127Processor Configuration Registers2.7.4 VC0RCAP—VC0 Resource Capability RegisterB/D/F/Type: 0/1/0–2/MMRAddress Offset: 110–113hR

Processor Configuration Registers128 Datasheet, Volume 22.7.5 VC0RCTL—VC0 Resource Control RegisterThis register controls the resources associated wit

Datasheet, Volume 2 129Processor Configuration Registers2.7.6 VC0RSTS—VC0 Resource Status RegisterThis register reports the Virtual Channel specific s

Datasheet, Volume 2 13Processor Configuration Registers2 Processor Configuration RegistersThis chapter contains the following:• Register terminology•

Processor Configuration Registers130 Datasheet, Volume 22.8 PCI Device 2 Configuration RegistersTable 2-10 lists the registers arranged by address off

Datasheet, Volume 2 131Processor Configuration Registers2.8.1 VID2—Vendor Identification RegisterThis register, combined with the Device Identificatio

Processor Configuration Registers132 Datasheet, Volume 22.8.3 PCICMD2—PCI Command RegisterThis 16-bit register provides basic control over the IGD&apo

Datasheet, Volume 2 133Processor Configuration Registers2.8.4 PCISTS2—PCI Status RegisterPCISTS is a 16-bit status register that reports the occurrenc

Processor Configuration Registers134 Datasheet, Volume 22.8.5 RID2—Revision Identification RegisterThis register contains the revision number for Devi

Datasheet, Volume 2 135Processor Configuration Registers2.8.7 CLS—Cache Line Size RegisterThe IGD does not support this register as a PCI slave.2.8.8

Processor Configuration Registers136 Datasheet, Volume 22.8.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address RegisterThis register

Datasheet, Volume 2 137Processor Configuration Registers2.8.11 GMADR—Graphics Memory Range Address RegisterGMADR is the PCI aperture used by software

Processor Configuration Registers138 Datasheet, Volume 22.8.12 IOBAR—I/O Base Address RegisterThis register provides the Base offset of the I/O regist

Datasheet, Volume 2 139Processor Configuration Registers2.8.14 SID2—Subsystem Identification RegisterThis register is used to uniquely identify the su

Processor Configuration Registers14 Datasheet, Volume 22.2 PCI Devices and Functions on ProcessorNote:1. Not all devices are enabled in all configurat

Processor Configuration Registers140 Datasheet, Volume 22.8.17 MINGNT—Minimum Grant RegisterThe Integrated Graphics Device has no requirement for the

Datasheet, Volume 2 141Processor Configuration Registers2.8.19 MSAC—Multi Size Aperture Control RegisterThis register determines the size of the graph

Processor Configuration Registers142 Datasheet, Volume 22.9 Device 2 I/O Registers2.9.1 INDEX—MMIO Address RegisterA 32-bit I/O write to this port loa

Datasheet, Volume 2 143Processor Configuration Registers2.10 PCI Device 6 Configuration RegistersTable 2-12 lists the registers arranged by address of

Processor Configuration Registers144 Datasheet, Volume 22.10.1 VID6—Vendor Identification RegisterThis register, combined with the Device Identificati

Datasheet, Volume 2 145Processor Configuration Registers2.10.2 DID6—Device Identification RegisterThis register, combined with the Vendor Identificati

Processor Configuration Registers146 Datasheet, Volume 26RW 0bUncoreParity Error Response Enable (PERRE)Controls whether or not the Master Data Parity

Datasheet, Volume 2 147Processor Configuration Registers2.10.4 PCISTS6—PCI Status RegisterThis register reports the occurrence of error conditions ass

Processor Configuration Registers148 Datasheet, Volume 28RW1C 0b UncoreMaster Data Parity Error (PMDPE)This bit is set by a Requester (Primary Side fo

Datasheet, Volume 2 149Processor Configuration Registers2.10.5 RID6—Revision Identification RegisterThis register contains the revision number of the

Datasheet, Volume 2 15Processor Configuration Registers2.3 System Address MapThe processor supports 512 GB (39 bit) of addressable memory space and 64

Processor Configuration Registers150 Datasheet, Volume 22.10.7 CL6—Cache Line Size Register2.10.8 HDR6—Header Type RegisterThis register identifies th

Datasheet, Volume 2 151Processor Configuration Registers2.10.10 SBUSN6—Secondary Bus Number RegisterThis register identifies the bus number assigned t

Processor Configuration Registers152 Datasheet, Volume 22.10.12 IOBASE6—I/O Base Address RegisterThis register controls the processor to PCI Express-G

Datasheet, Volume 2 153Processor Configuration Registers2.10.14 SSTS6—Secondary Status RegisterSSTS is a 16-bit status register that reports the occur

Processor Configuration Registers154 Datasheet, Volume 22.10.15 MBASE6—Memory Base Address RegisterThis register controls the processor to PCI Express

Datasheet, Volume 2 155Processor Configuration Registers2.10.16 MLIMIT6—Memory Limit Address RegisterThis register controls the processor to PCI Expre

Processor Configuration Registers156 Datasheet, Volume 22.10.17 PMBASE6—Prefetchable Memory Base Address RegisterThis register, in conjunction with th

Datasheet, Volume 2 157Processor Configuration Registers2.10.18 PMLIMIT6—Prefetchable Memory Limit Address RegisterThis register, in conjunction with

Processor Configuration Registers158 Datasheet, Volume 22.10.19 PMBASEU6—Prefetchable Memory Base Address Upper RegisterThe functionality associated w

Datasheet, Volume 2 159Processor Configuration Registers2.10.20 PMLIMITU6—Prefetchable Memory Limit Address Upper RegisterThe functionality associated

Processor Configuration Registers16 Datasheet, Volume 2• Device 6, Function 0— MBASE/MLIMIT – PCI Express port non-prefetchable memory access window.

Processor Configuration Registers160 Datasheet, Volume 22.10.22 INTRLINE6—Interrupt Line RegisterThis register contains interrupt line routing informa

Datasheet, Volume 2 161Processor Configuration Registers2.10.24 BCTRL6—Bridge Control RegisterThis register provides extensions to the PCICMD register

Processor Configuration Registers162 Datasheet, Volume 21RW 0bUncoreSERR Enable (SERREN)0 = No forwarding of error messages from secondary side to pri

Datasheet, Volume 2 163Processor Configuration Registers2.10.25 PM_CAPID6—Power Management Capabilities RegisterB/D/F/Type: 0/6/0/PCIAddress Offset: 8

Processor Configuration Registers164 Datasheet, Volume 22.10.26 PM_CS6—Power Management Control/Status RegisterB/D/F/Type: 0/6/0/PCIAddress Offset: 84

Datasheet, Volume 2 165Processor Configuration Registers2.10.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities RegisterThis capability is used to un

Processor Configuration Registers166 Datasheet, Volume 22.10.28 SS—Subsystem ID and Subsystem Vendor ID RegisterSystem BIOS can be used as the mechani

Datasheet, Volume 2 167Processor Configuration Registers2.10.30 MC—Message Control RegisterSystem software can modify bits in this register, but the d

Processor Configuration Registers168 Datasheet, Volume 22.10.31 MA—Message Address Register2.10.32 MD—Message Data Register2.10.33 PEG_CAPL—PCI Expres

Datasheet, Volume 2 169Processor Configuration Registers2.10.34 PEG_CAP—PCI Express-G Capabilities RegisterThis register indicates PCI Express device

Datasheet, Volume 2 17Processor Configuration RegistersFigure 2-1. System Address Range Example Main Memory Add RangeOS VISIBLE< 4 GBPCI Memory Add

Processor Configuration Registers170 Datasheet, Volume 22.10.36 DCTL—Device Control RegisterThis register provides control for PCI Express device spec

Datasheet, Volume 2 171Processor Configuration Registers2.10.37 DSTS—Device Status RegisterThis register reflects status corresponding to controls in

Processor Configuration Registers172 Datasheet, Volume 22.10.38 LCTL—Link Control RegisterThis register allows control of PCI Express link.B/D/F/Type:

Datasheet, Volume 2 173Processor Configuration Registers6 RW 0b UncoreCommon Clock Configuration (CCC)0 = Indicates that this component and the compon

Processor Configuration Registers174 Datasheet, Volume 22.10.39 LSTS—Link Status RegisterThis register indicates PCI Express link status.B/D/F/Type: 0

Datasheet, Volume 2 175Processor Configuration Registers2.10.40 SLOTCAP—Slot Capabilities RegisterPCI Express Slot related registers allow for the sup

Processor Configuration Registers176 Datasheet, Volume 216:15 RW-O 00b UncoreSlot Power Limit Scale (SPLS)This field specifies the scale used for the

Datasheet, Volume 2 177Processor Configuration Registers2.10.41 SLOTCTL—Slot Control RegisterPCI Express Slot related registers allow for the support

Processor Configuration Registers178 Datasheet, Volume 27:6 RO 00b UncoreReserved for Attention Indicator Control (AIC)If an Attention Indicator is im

Datasheet, Volume 2 179Processor Configuration Registers2.10.42 SLOTSTS—Slot Status RegisterThis is for PCI Express Slot related registers.B/D/F/Type:

Processor Configuration Registers18 Datasheet, Volume 22.3.1 Legacy Address RangeThis area is divided into the following address regions:• 0–640 KB –

Processor Configuration Registers180 Datasheet, Volume 22.10.43 RCTL—Root Control RegisterThis register allows control of PCI Express Root Complex spe

Datasheet, Volume 2 181Processor Configuration Registers2.11 PCI Device 6 Extended Configuration RegistersTable 2-13 lists the registers arranged by a

Processor Configuration Registers182 Datasheet, Volume 22.11.2 PVCCAP2—Port VC Capability Register 2This register describes the configuration of PCI E

Datasheet, Volume 2 183Processor Configuration Registers2.11.4 VC0RCAP—VC0 Resource Capability RegisterB/D/F/Type: 0/6/0/MMRAddress Offset: 110–113hRe

Processor Configuration Registers184 Datasheet, Volume 22.11.5 VC0RCTL—VC0 Resource Control RegisterThis register controls the resources associated wi

Datasheet, Volume 2 185Processor Configuration Registers2.11.6 VC0RSTS—VC0 Resource Status RegisterThis register reports the Virtual Channel specific

Processor Configuration Registers186 Datasheet, Volume 22.12 DMIBAR RegistersTable 2-14 lists the registers arranged by address offset. Register bit d

Datasheet, Volume 2 187Processor Configuration Registers2.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability RegisterThis register indicates DMI Vi

Processor Configuration Registers188 Datasheet, Volume 22.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1This register describes the configuration o

Datasheet, Volume 2 189Processor Configuration Registers2.12.4 DMIPVCCTL—DMI Port VC Control Register2.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Reg

Datasheet, Volume 2 19Processor Configuration Registers2.3.1.2 Legacy Video Area (A_0000h–B_FFFFh)The legacy 128 KB VGA memory range, frame buffer, (0

Processor Configuration Registers190 Datasheet, Volume 22.12.6 DMIVC0RCTL—DMI VC0 Resource Control RegisterThis register controls the resources associ

Datasheet, Volume 2 191Processor Configuration Registers2.12.7 DMIVC0RSTS—DMI VC0 Resource Status RegisterThis register reports the Virtual Channel sp

Processor Configuration Registers192 Datasheet, Volume 22.12.9 DMIVC1RCTL—DMI VC1 Resource Control RegisterThis register controls the resources associ

Datasheet, Volume 2 193Processor Configuration Registers2.12.10 DMIVC1RSTS—DMI VC1 Resource Status RegisterThis register reports the Virtual Channel s

Processor Configuration Registers194 Datasheet, Volume 22.12.12 DMIVCPRCTL—DMI VCp Resource Control RegisterThis register controls the resources assoc

Datasheet, Volume 2 195Processor Configuration Registers2.12.13 DMIVCPRSTS—DMI VCp Resource Status RegisterThis register reports the Virtual Channel s

Processor Configuration Registers196 Datasheet, Volume 22.12.14 DMIESD—DMI Element Self Description RegisterThis register provides information about t

Datasheet, Volume 2 197Processor Configuration Registers2.12.15 DMILE1D—DMI Link Entry 1 Description RegisterThis register provides the first part of

Processor Configuration Registers198 Datasheet, Volume 22.12.17 DMILE2D—DMI Link Entry 2 Description RegisterThis register provides the first part of

Datasheet, Volume 2 199Processor Configuration Registers2.12.19 LCAP—Link Capabilities RegisterThis register indicates DMI specific capabilities.B/D/F

2 Datasheet, Volume 2Legal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMP

Processor Configuration Registers20 Datasheet, Volume 22.3.1.3 PAM (C_0000h–F_FFFFh)The 13 sections from 768 KB to 1 MB comprise what is also known as

Processor Configuration Registers200 Datasheet, Volume 22.12.20 LCTL—Link Control RegisterThis register allows control of PCI Express link.B/D/F/Type:

Datasheet, Volume 2 201Processor Configuration Registers2.12.21 LSTS—DMI Link Status RegisterThis register indicates DMI status.B/D/F/Type: 0/0/0/DMIB

Processor Configuration Registers202 Datasheet, Volume 22.12.22 LCTL2—Link Control 2 RegisterB/D/F/Type: 0/0/0/DMIBARAddress Offset: 98–99hReset Value

Datasheet, Volume 2 203Processor Configuration Registers6RWS 0bPowergoodSelectable De-emphasis (selectabledeemphasis)When the Link is operating at 5 G

Processor Configuration Registers204 Datasheet, Volume 22.12.23 LSTS2—Link Status 2 Register2.12.24 AFE_BMUF0—AFE BMU Configuration Function 0 Registe

Datasheet, Volume 2 205Processor Configuration Registers2.13 MCHBAR Registers in Memory Controller – Channel 0 Table 2-15 lists the registers arranged

Processor Configuration Registers206 Datasheet, Volume 22.13.2 TC_RAP_C0—Timing of DDR Regular Access Parameters RegisterThis register provides the re

Datasheet, Volume 2 207Processor Configuration Registers2.13.4 TC_SRFTP_C0—Self-Refresh Timing Parameters RegisterThis register provides Self-refresh

Processor Configuration Registers208 Datasheet, Volume 22.13.6 TC_RFP_C0—Refresh Parameters Register2.13.7 TC_RFTP_C0—Refresh Timing Parameters Regist

Datasheet, Volume 2 209Processor Configuration Registers2.14 MCHBAR Registers in Memory Controller – Channel 1Table 2-16 lists the registers arranged

Datasheet, Volume 2 21Processor Configuration Registers2.3.2.1 ISA Hole (15 MB–16 MB)The ISA Hole is enabled in the Legacy Access Control Register in

Processor Configuration Registers210 Datasheet, Volume 22.14.2 TC_RAP_C1—Timing of DDR Regular Access Parameters RegisterThis register provides the re

Datasheet, Volume 2 211Processor Configuration Registers2.14.4 TC_SRFTP_C1—Self-Refresh Timing Parameters RegisterThis register provides Self-refresh

Processor Configuration Registers212 Datasheet, Volume 22.14.6 TC_RFP_C1—Refresh Parameters Register2.14.7 TC_RFTP_C1—Refresh Timing Parameters Regist

Datasheet, Volume 2 213Processor Configuration Registers2.15 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub (IMPH)Table 2-17

Processor Configuration Registers214 Datasheet, Volume 22.16 MCHBAR Registers in Memory Controller – CommonTable 2-18 lists the registers arranged by

Datasheet, Volume 2 215Processor Configuration Registers2.16.2 MAD_DIMM_ch0—Address Decode Channel 0 RegisterThis register defines channel characteris

Processor Configuration Registers216 Datasheet, Volume 22.16.3 MAD_DIMM_ch1—Address Decode Channel 1 RegisterThis register defines channel characteris

Datasheet, Volume 2 217Processor Configuration Registers2.16.4 PM_SREF_config—Self Refresh Configuration RegisterThis self refresh mode control regist

Processor Configuration Registers218 Datasheet, Volume 22.17 Memory Controller MMIO Registers Broadcast GroupTable 2-19 lists the registers arranged b

Datasheet, Volume 2 219Processor Configuration Registers2.17.2 PM_CMD_PWR—Power Management Command Power RegisterThis register defines the power contr

Processor Configuration Registers22 Datasheet, Volume 2for managing DMA accesses to addresses above 4 GB. DMA-remapping hardware implementations on pl

Processor Configuration Registers220 Datasheet, Volume 22.18 Integrated Graphics VT-d Remapping Engine RegistersTable 2-20 lists the registers arrange

Datasheet, Volume 2 221Processor Configuration Registers2.18.1 VER_REG—Version RegisterThis register reports the architecture version supported. Backw

Processor Configuration Registers222 Datasheet, Volume 22.18.2 CAP_REG—Capability RegisterThis register reports general remapping hardware capabilitie

Datasheet, Volume 2 223Processor Configuration Registers23 RO 1b UncoreIsochrony (ISOCH)0 = Remapping hardware unit has no critical isochronous reques

Processor Configuration Registers224 Datasheet, Volume 27RO 0bUncoreCaching Mode (CM)0 = Not-present and erroneous entries are not cached in any of th

Datasheet, Volume 2 225Processor Configuration Registers2.18.3 ECAP_REG—Extended Capability RegisterThis register reports remapping hardware extended

Processor Configuration Registers226 Datasheet, Volume 22.18.4 GCMD_REG—Global Command RegisterThis register controls remapping hardware. If multiple

Datasheet, Volume 2 227Processor Configuration Registers30 WO 0b UncoreSet Root Table Pointer (SRTP)Software sets this field to set/update the root-en

Processor Configuration Registers228 Datasheet, Volume 227 RO 0b UncoreWrite Buffer Flush (WBF)This bit is valid only for implementations requiring wr

Datasheet, Volume 2 229Processor Configuration Registers24 WO 0b UncoreSet Interrupt Remap Table Pointer (SIRTP)This field is valid only for implement

Datasheet, Volume 2 23Processor Configuration Registers2.3.2.6 Graphics Stolen Spaces2.3.2.6.1 GTT Stolen Memory Space (GSM)GSM is allocated to store

Processor Configuration Registers230 Datasheet, Volume 22.18.5 GSTS_REG—Global Status RegisterThis register reports general remapping hardware status.

Datasheet, Volume 2 231Processor Configuration Registers2.18.6 RTADDR_REG—Root-Entry Table Address RegisterThis register provides the base address of

Processor Configuration Registers232 Datasheet, Volume 22.18.7 CCMD_REG—Context Command RegisterThis register manages context cache. The act of writin

Datasheet, Volume 2 233Processor Configuration Registers60:59 RO-V 1h UncoreContext Actual Invalidation Granularity (CAIG)Hardware reports the granula

Processor Configuration Registers234 Datasheet, Volume 22.18.8 FSTS_REG—Fault Status RegisterThis register indicates the various error status.B/D/F/Ty

Datasheet, Volume 2 235Processor Configuration Registers1ROS-V 0bPowergoodPrimary Pending Fault (PPF)This bit indicates if there are one or more pendi

Processor Configuration Registers236 Datasheet, Volume 22.18.9 FECTL_REG—Fault Event Control RegisterThis register specifies the fault event interrupt

Datasheet, Volume 2 237Processor Configuration Registers2.18.10 FEDATA_REG—Fault Event Data RegisterThis register specifies the interrupt message data

Processor Configuration Registers238 Datasheet, Volume 22.18.13 AFLOG_REG—Advanced Fault Log RegisterThis register specifies the base address of the m

Datasheet, Volume 2 239Processor Configuration Registers2.18.14 PMEN_REG—Protected Memory Enable RegisterThis register enables the DMA-protected memor

Processor Configuration Registers24 Datasheet, Volume 2There are sub-ranges within the PCI Memory address range defined as APIC Configuration Space, M

Processor Configuration Registers240 Datasheet, Volume 22.18.15 PLMBASE_REG—Protected Low-Memory Base RegisterThis register sets up the base address o

Datasheet, Volume 2 241Processor Configuration Registers2.18.16 PLMLIMIT_REG—Protected Low-Memory Limit RegisterThis register sets up the limit addres

Processor Configuration Registers242 Datasheet, Volume 22.18.17 PHMBASE_REG—Protected High-Memory Base RegisterThis register sets up the base address

Datasheet, Volume 2 243Processor Configuration Registers2.18.18 PHMLIMIT_REG—Protected High-Memory Limit RegisterThis register sets up the limit addre

Processor Configuration Registers244 Datasheet, Volume 22.18.19 IQH_REG—Invalidation Queue Head RegisterThis register indicates the invalidation queue

Datasheet, Volume 2 245Processor Configuration Registers2.18.21 IQA_REG—Invalidation Queue Address RegisterThis register configures the base address a

Processor Configuration Registers246 Datasheet, Volume 22.18.23 IECTL_REG—Invalidation Event Control RegisterThis register specifies the invalidation

Datasheet, Volume 2 247Processor Configuration Registers2.18.24 IEDATA_REG—Invalidation Event Data RegisterThis register specifies the Invalidation Ev

Processor Configuration Registers248 Datasheet, Volume 22.18.26 IRTA_REG—Interrupt Remapping Table Address RegisterThis register provides the base add

Datasheet, Volume 2 249Processor Configuration Registers2.18.27 IVA_REG—Invalidate Address RegisterThis register provides the DMA address whose corres

Datasheet, Volume 2 25Processor Configuration Registers2.3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh)This range is reserved for APIC configu

Processor Configuration Registers250 Datasheet, Volume 22.18.28 IOTLB_REG—IOTLB Invalidate RegisterThis register invalidates the IOTLB. The act of wri

Datasheet, Volume 2 251Processor Configuration Registers58:57 RO-V 1h UncoreIOTLB Actual Invalidation Granularity (IAIG)Hardware reports the granulari

Processor Configuration Registers252 Datasheet, Volume 22.18.29 FRCDL_REG—Fault Recording Low RegisterThis register records fault information when pri

Datasheet, Volume 2 253Processor Configuration Registers2.18.30 FRCDH_REG—Fault Recording High RegisterThis register records fault information when pr

Processor Configuration Registers254 Datasheet, Volume 22.18.31 VTPOLICY—DMA Remap Engine Policy Control RegisterThis register contains all the policy

Datasheet, Volume 2 255Processor Configuration Registers2.19 PCU MCHBAR RegistersTable 2-21 lists the registers arranged by address offset. Register b

Processor Configuration Registers256 Datasheet, Volume 22.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory ThermalEstimation Configuration RegisterThis register

Datasheet, Volume 2 257Processor Configuration Registers2.19.2 MEM_TRML_THRESHOLDS_CONFIG—Memory Thermal Thresholds Configuration RegisterThis registe

Processor Configuration Registers258 Datasheet, Volume 22.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal Status Report RegisterThis register reports the t

Datasheet, Volume 2 259Processor Configuration Registers2.19.4 MEM_TRML_TEMPERATURE_REPORT—Memory ThermalTemperature Report RegisterThis register is u

Processor Configuration Registers26 Datasheet, Volume 22.3.4 Main Memory Address Space (4 GB to TOUUD)The processor supports 39-bit addressing. The ma

Processor Configuration Registers260 Datasheet, Volume 22.19.6 GT_PERF_STATUS—GT Performance Status RegisterP-state encoding for the Secondary Power P

Datasheet, Volume 2 261Processor Configuration Registers2.19.8 SSKPD—Sticky Scratchpad Data RegisterThis register holds 64 writable bits with no funct

Processor Configuration Registers262 Datasheet, Volume 213:8 RWS 000000bPowergoodSelf Refresh Latency Time (WM1)Number of microseconds to access memor

Datasheet, Volume 2 263Processor Configuration Registers2.20 PXPEPBAR RegistersTable 2-22 lists the registers arranged by address offset. Register bit

Processor Configuration Registers264 Datasheet, Volume 22.21 Default PEG/DMI VT-d Remapping Engine RegistersTable 2-23 lists the registers arranged by

Datasheet, Volume 2 265Processor Configuration Registers2.21.1 VER_REG—Version RegisterThis register reports the architecture version supported. Backw

Processor Configuration Registers266 Datasheet, Volume 22.21.2 CAP_REG—Capability RegisterThis register reports general remapping hardware capabilitie

Datasheet, Volume 2 267Processor Configuration Registers23 RO 0b UncoreIsochrony (ISOCH)0 = Remapping hardware unit has no critical isochronous reques

Processor Configuration Registers268 Datasheet, Volume 27RO 0bUncoreCaching Mode (CM)0 = Not-present and erroneous entries are Not cached in any of th

Datasheet, Volume 2 269Processor Configuration Registers2.21.3 ECAP_REG—Extended Capability RegisterThis register reports remapping hardware extended

Datasheet, Volume 2 27Processor Configuration Registers2.3.4.1 Memory Re-claim BackgroundThe following are examples of Memory Mapped IO devices that a

Processor Configuration Registers270 Datasheet, Volume 22.21.4 GCMD_REG—Global Command RegisterThis register controls remapping hardware. If multiple

Datasheet, Volume 2 271Processor Configuration Registers30 WO 0b UncoreSet Root Table Pointer (SRTP)Software sets this field to set/update the root-en

Processor Configuration Registers272 Datasheet, Volume 227 RO 0b UncoreWrite Buffer Flush (WBF)This bit is valid only for implementations requiring wr

Datasheet, Volume 2 273Processor Configuration Registers24 WO 0b UncoreSet Interrupt Remap Table Pointer (SIRTP)This field is valid only for implement

Processor Configuration Registers274 Datasheet, Volume 22.21.5 GSTS_REG—Global Status RegisterThis register reports general remapping hardware status.

Datasheet, Volume 2 275Processor Configuration Registers2.21.6 RTADDR_REG—Root-Entry Table Address RegisterThis register provides the base address of

Processor Configuration Registers276 Datasheet, Volume 22.21.7 CCMD_REG—Context Command RegisterThis register manages context cache. The act of writin

Datasheet, Volume 2 277Processor Configuration Registers60:59 RO-V 0h UncoreContext Actual Invalidation Granularity (CAIG)Hardware reports the granula

Processor Configuration Registers278 Datasheet, Volume 22.21.8 FSTS_REG—Fault Status RegisterThis register indicates the various error status.B/D/F/Ty

Datasheet, Volume 2 279Processor Configuration Registers1ROS-V 0bPowergoodPrimary Pending Fault (PPF)This field indicates if there are one or more pen

Processor Configuration Registers28 Datasheet, Volume 22.3.4.3 Memory RemappingAn incoming address (referred to as a logical address) is checked to se

Processor Configuration Registers280 Datasheet, Volume 22.21.9 FECTL_REG—Fault Event Control RegisterThis register specifies the fault event interrupt

Datasheet, Volume 2 281Processor Configuration Registers2.21.10 FEDATA_REG—Fault Event Data RegisterThis register specifies the interrupt message data

Processor Configuration Registers282 Datasheet, Volume 22.21.13 AFLOG_REG—Advanced Fault Log RegisterThis register specifies the base address of the m

Datasheet, Volume 2 283Processor Configuration Registers2.21.14 PMEN_REG—Protected Memory Enable RegisterThis register enables the DMA-protected memor

Processor Configuration Registers284 Datasheet, Volume 22.21.15 PLMBASE_REG—Protected Low-Memory Base RegisterThis register sets up the base address o

Datasheet, Volume 2 285Processor Configuration Registers2.21.16 PLMLIMIT_REG—Protected Low-Memory Limit RegisterThis register sets up the limit addres

Processor Configuration Registers286 Datasheet, Volume 22.21.17 PHMBASE_REG—Protected High-Memory Base RegisterThis register sets up the base address

Datasheet, Volume 2 287Processor Configuration Registers2.21.18 PHMLIMIT_REG—Protected High-Memory Limit RegisterThis register sets up the limit addre

Processor Configuration Registers288 Datasheet, Volume 22.21.19 IQH_REG—Invalidation Queue Head RegisterRegister indicating the invalidation queue hea

Datasheet, Volume 2 289Processor Configuration Registers2.21.21 IQA_REG—Invalidation Queue Address RegisterThis register configures the base address a

Datasheet, Volume 2 29Processor Configuration RegistersCase 1 – Less than 4 GB of Physical Memory (no remap)• Populated Physical Memory = 2 GB• Addres

Processor Configuration Registers290 Datasheet, Volume 22.21.23 IECTL_REG—Invalidation Event Control RegisterThis register specifies the invalidation

Datasheet, Volume 2 291Processor Configuration Registers2.21.24 IEDATA_REG—Invalidation Event Data RegisterThis register specifies the Invalidation Ev

Processor Configuration Registers292 Datasheet, Volume 22.21.26 IEUADDR_REG—Invalidation Event Upper Address RegisterThis register specifies the Inval

Datasheet, Volume 2 293Processor Configuration Registers2.21.28 IVA_REG—Invalidate Address RegisterThis register provides the DMA address whose corres

Processor Configuration Registers294 Datasheet, Volume 22.21.29 IOTLB_REG—IOTLB Invalidate RegisterRegister to invalidate IOTLB. The act of writing th

Datasheet, Volume 2 295Processor Configuration Registers§ §58:57 RO-V 0h UncoreIOTLB Actual Invalidation Granularity (IAIG)Hardware reports the granul

Processor Configuration Registers296 Datasheet, Volume 2

Datasheet, Volume 2 3Contents1Introduction...

Processor Configuration Registers30 Datasheet, Volume 2Case 2 – Greater than 4 GB of Physical MemoryIn this case the amount of memory remapped is the

Datasheet, Volume 2 31Processor Configuration RegistersThe Remap window is inclusive of the Base and Limit addresses. In the decoder A[19:0] of the Re

Processor Configuration Registers32 Datasheet, Volume 2Implementation Notes• Remap applies to transactions from all interfaces. All upstream PEG/DMI t

Datasheet, Volume 2 33Processor Configuration Registers2.3.6 PCI Express* Graphics Attach (PEG)The processor can be programmed to direct memory access

Processor Configuration Registers34 Datasheet, Volume 22.3.7 Graphics Memory Address RangesThe MCH can be programmed to direct memory accesses to IGD

Datasheet, Volume 2 35Processor Configuration Registers2.3.8 System Management Mode (SMM)Unlike FSB platforms, the Core handles all SMM mode transacti

Processor Configuration Registers36 Datasheet, Volume 2display initiated LP non-snoop writes (for display writing a KVM captured frame) to Intel ME st

Datasheet, Volume 2 37Processor Configuration RegistersThe effective size of the range is programmed by the plug-and-play configuration software and i

Processor Configuration Registers38 Datasheet, Volume 2I/O cycles and configuration cycles are not supported in the upstream direction. The result wil

Datasheet, Volume 2 39Processor Configuration Registers— No “pacer” arbitration or TWRR arbitration will occur. Never remaps to different port. (PCH t

4 Datasheet, Volume 22.5.8 SVID—Subsystem Vendor Identification Register...542.5.9 SID—Subsystem Identification Reg

Processor Configuration Registers40 Datasheet, Volume 22.3.13.2 PCI Express* Interface Decode RulesAll “SNOOP semantic” PCI Express transactions are k

Datasheet, Volume 2 41Processor Configuration Registers2.3.13.3 Legacy VGA and I/O Range Decode RulesThe legacy 128 KB VGA memory range 000A_0000h-000

Processor Configuration Registers42 Datasheet, Volume 2Accesses to the VGA memory range are directed to IGD depend on the configuration. The configura

Datasheet, Volume 2 43Processor Configuration RegistersFor regions mapped outside of the IGD (or if IGD is disabled), the legacy VGA memory range A000

Processor Configuration Registers44 Datasheet, Volume 2Enable bit is not set. If the VGA enable bit is set, then accesses to I/O address range x3BCh–x

Datasheet, Volume 2 45Processor Configuration Registers2.4 Processor Register IntroductionThe processor contains two sets of software accessible regis

Processor Configuration Registers46 Datasheet, Volume 22.4.1 I/O Mapped RegistersThe processor contains two registers that reside in the processor I/O

Datasheet, Volume 2 47Processor Configuration Registers81h PAM1 Programmable Attribute Map 1 00h RW82h PAM2 Programmable Attribute Map 2 00h RW83h P

Processor Configuration Registers48 Datasheet, Volume 22.5.1 VID—Vendor Identification RegisterThis register, combined with the Device Identification

Datasheet, Volume 2 49Processor Configuration Registers2.5.3 PCICMD—PCI Command RegisterSince Device 0 does not physically reside on PCI_A, many of th

Datasheet, Volume 2 52.6.30 MC—Message Control Register ... 1082.6.31 MA—Message Address Regi

Processor Configuration Registers50 Datasheet, Volume 22.5.4 PCISTS—PCI Status RegisterThis status register reports the occurrence of error events on

Datasheet, Volume 2 51Processor Configuration Registers8 RW1C 0b UncoreMaster Data Parity Error Detected (DPD)This bit is set when DMI received a Pois

Processor Configuration Registers52 Datasheet, Volume 22.5.5 RID—Revision Identification RegisterThis register contains the revision number of Device

Datasheet, Volume 2 53Processor Configuration Registers2.5.6 CC—Class Code RegisterThis register identifies the basic function of the device, a more s

Processor Configuration Registers54 Datasheet, Volume 22.5.8 SVID—Subsystem Vendor Identification RegisterThis value is used to identify the vendor of

Datasheet, Volume 2 55Processor Configuration Registers2.5.10 PXPEPBAR—PCI Express Egress Port Base Address RegisterThis is the base address for the P

Processor Configuration Registers56 Datasheet, Volume 22.5.11 MCHBAR—Host Memory Mapped Register Range Base RegisterThis is the base address for the H

Datasheet, Volume 2 57Processor Configuration Registers2.5.12 GGC—GMCH Graphics Control Register RegisterAll the bits in this register are Intel TXT l

Processor Configuration Registers58 Datasheet, Volume 22RO 0h Reserved1RW-L 0bUncoreIGD VGA Disable (IVD)0 = Enable. Device 2 (IGD) claims VGA memory

Datasheet, Volume 2 59Processor Configuration Registers2.5.13 DEVEN—Device Enable RegisterThis register allows for enabling/disabling of PCI devices a

6 Datasheet, Volume 22.10.9 PBUSN6—Primary Bus Number Register...1502.10.10 SBUSN6—Secondary Bus Number R

Processor Configuration Registers60 Datasheet, Volume 22.5.14 PCIEXBAR—PCI Express Register Range Base Address RegisterThis is the base address for th

Datasheet, Volume 2 61Processor Configuration RegistersB/D/F/Type: 0/0/0/PCIAddress Offset: 60–67hReset Value: 0000_0000_0000_0000hAccess: RW, RW-VSiz

Processor Configuration Registers62 Datasheet, Volume 22.5.15 DMIBAR—Root Complex Register Range Base Address RegisterThis is the base address for the

Datasheet, Volume 2 63Processor Configuration Registers2.5.16 PAM0—Programmable Attribute Map 0 RegisterThis register controls the read, write and sha

Processor Configuration Registers64 Datasheet, Volume 22.5.17 PAM1—Programmable Attribute Map 1 RegisterThis register controls the read, write and sha

Datasheet, Volume 2 65Processor Configuration Registers2.5.18 PAM2—Programmable Attribute Map 2 RegisterThis register controls the read, write and sha

Processor Configuration Registers66 Datasheet, Volume 22.5.19 PAM3—Programmable Attribute Map 3 RegisterThis register controls the read, write and sha

Datasheet, Volume 2 67Processor Configuration Registers2.5.20 PAM4—Programmable Attribute Map 4 RegisterThis register controls the read, write and sha

Processor Configuration Registers68 Datasheet, Volume 22.5.21 PAM5—Programmable Attribute Map 5 RegisterThis register controls the read, write and sha

Datasheet, Volume 2 69Processor Configuration Registers2.5.22 PAM6—Programmable Attribute Map 6 RegisterThis register controls the read, write and sha

Datasheet, Volume 2 72.12.14 DMIESD—DMI Element Self Description Register ... 1962.12.15 DMILE1D—DMI Link Entry 1 Desc

Processor Configuration Registers70 Datasheet, Volume 22.5.23 LAC—Legacy Access Control RegisterThis 8-bit register controls steering of MDA cycles an

Datasheet, Volume 2 71Processor Configuration Registers2 RW 0b UncorePEG12 MDA Present (MDAP12)This bit works with the VGA Enable bits in the BCTRL re

Processor Configuration Registers72 Datasheet, Volume 21RW 0bUncorePEG11 MDA Present (MDAP11)This bit works with the VGA Enable bits in the BCTRL regi

Datasheet, Volume 2 73Processor Configuration Registers0 RW 0b UncorePEG10 MDA Present (MDAP10)This bit works with the VGA Enable bits in the BCTRL re

Processor Configuration Registers74 Datasheet, Volume 22.5.24 REMAPBASE—Remap Base Address Register2.5.25 REMAPLIMIT—Remap Limit Address RegisterB/D/F

Datasheet, Volume 2 75Processor Configuration Registers2.5.26 TOM—Top of Memory RegisterThis register contains the size of physical memory. BIOS deter

Processor Configuration Registers76 Datasheet, Volume 22.5.27 TOUUD—Top of Upper Usable DRAM RegisterThis 64-bit register defines the Top of Upper Usa

Datasheet, Volume 2 77Processor Configuration Registers2.5.28 BDSM—Base Data of Stolen Memory RegisterThis register contains the base address of graph

Processor Configuration Registers78 Datasheet, Volume 22.5.30 G Memory Base RegisterThis register contains the base address of TSEG DRAM memory. BIOS

Datasheet, Volume 2 79Processor Configuration Registers2.5.31 TOLUD—Top of Low Usable DRAM RegisterThis 32 bit register defines the Top of Low Usable

8 Datasheet, Volume 22.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register ...2412.18.17 PHMBASE_REG—Protected High-Memory

Processor Configuration Registers80 Datasheet, Volume 22.5.32 SKPD—Scratchpad Data RegisterThis register holds 32 writable bits with no functionality

Datasheet, Volume 2 81Processor Configuration Registers2.5.33 CAPID0_A—Capabilities A RegisterThis register control of bits in this register are only

Processor Configuration Registers82 Datasheet, Volume 27:4 RO-FW 0h Reserved 3:3 RO 0h Reserved 2:0 RO-FW 000b UncoreDDR3 Maximum Frequency Capability

Datasheet, Volume 2 83Processor Configuration Registers2.6 PCI Device 1, Function 0–2 Configuration RegistersTable 2-8 lists the registers arranged by

Processor Configuration Registers84 Datasheet, Volume 290–91h MSI_CAPID Message Signaled Interrupts Capability ID A005h RO92–93h MC Message Control 00

Datasheet, Volume 2 85Processor Configuration Registers2.6.1 VID1—Vendor Identification RegisterThis register combined with the Device Identification

Processor Configuration Registers86 Datasheet, Volume 22.6.3 PCICMD1—PCI Command RegisterB/D/F/Type: 0/1/0–2/PCIAddress Offset: 4–5hReset Value: 0000h

Datasheet, Volume 2 87Processor Configuration Registers2 RW 0b UncoreBus Master Enable (BME)This bit controls the ability of the PEG port to forward M

Processor Configuration Registers88 Datasheet, Volume 22.6.4 PCISTS1—PCI Status RegisterThis register reports the occurrence of error conditions assoc

Datasheet, Volume 2 89Processor Configuration Registers8 RW1C 0b UncoreMaster Data Parity Error (PMDPE)This bit is Set by a Requester (Primary Side fo

Datasheet, Volume 2 92.21.27 IRTA_REG—Interrupt Remapping Table Address Register... 2922.21.28 IVA_REG—Invalidate Address Registe

Processor Configuration Registers90 Datasheet, Volume 22.6.5 RID1—Revision Identification RegisterThis register contains the revision number of the pr

Datasheet, Volume 2 91Processor Configuration Registers2.6.7 CL1—Cache Line Size Register2.6.8 HDR1—Header Type RegisterThis register identifies the h

Processor Configuration Registers92 Datasheet, Volume 22.6.10 SBUSN1—Secondary Bus Number RegisterThis register identifies the bus number assigned to

Datasheet, Volume 2 93Processor Configuration Registers2.6.12 IOBASE1—I/O Base Address RegisterThis register controls the processor to PCI Express-G I

Processor Configuration Registers94 Datasheet, Volume 22.6.14 SSTS1—Secondary Status RegisterSSTS is a 16-bit status register that reports the occurre

Datasheet, Volume 2 95Processor Configuration Registers2.6.15 MBASE1—Memory Base Address RegisterThis register controls the processor to PCI Express-G

Processor Configuration Registers96 Datasheet, Volume 22.6.16 MLIMIT1—Memory Limit Address RegisterThis register controls the processor to PCI Express

Datasheet, Volume 2 97Processor Configuration Registers2.6.17 PMBASE1—Prefetchable Memory Base Address RegisterThis register in conjunction with the c

Processor Configuration Registers98 Datasheet, Volume 22.6.18 PMLIMIT1—Prefetchable Memory Limit Address RegisterThis register in conjunction with the

Datasheet, Volume 2 99Processor Configuration Registers2.6.19 PMBASEU1—Prefetchable Memory Base Address Upper RegisterThe functionality associated wit