
Introduction
12 Datasheet, Volume 2
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Datasheet, Volume 2
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Legal Lines and Disclaimers
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Contents
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4 Datasheet, Volume 2
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Datasheet, Volume 2 5
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Revision History
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1 Introduction
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Introduction
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2 Processor Configuration
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2.3 System Address Map
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HOST/SYSTEM VIEW
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PHYSICAL MEMORY
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(DRAM CONTROLLER VIEW)
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2.3.1 Legacy Address Range
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2.3.2.2 TSEG
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2.3.2.5 Pre-allocated Memory
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2.3.3.4 High BIOS Area
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2.3.4.3 Memory Remapping
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2.3.4.5 Programming Model
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2.3.11 I/O Address Space
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2.4.1 I/O Mapped Registers
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2.5.6 CC—Class Code Register
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2.5.30 G Memory Base Register
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2.6.6 CC1—Class Code Register
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Register
100
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2RW 0bUncore
102
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Port Command Register
111
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5RW-V 0bUncore
114
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Configuration Registers
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108–10Bh
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(16 bytes)
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10C–10Dh
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110–113h
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23 RO 0h Reserved
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114–117h
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11A–11Bh
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208–20Bhh
129
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2.8.6 CC—Class Code Register
134
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Mapped Range Address Register
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27 RW-L 0b
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26:4 RO 000000h Uncore
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Device uses INTA#
139
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2.9 Device 2 I/O Registers
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PCI device
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2 RW 0b Uncore
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5 RW-V 0b Uncore
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104–107h
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2.12 DMIBAR Registers
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23:8 RO 0h Reserved
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Declaration Capability
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BC0–BC3h
204
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BCC–BCGh
204
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Channel 0
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4294-4297h
208
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4298-429Bh
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Channel 1
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4694–4697h
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4698–469Bh
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PEG/DMI/GSA streams
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5004–5007h
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5008–500Bh
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5060–5063h
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Register Symbol Register Name
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4CB0-4CB3h
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Registers
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100–107h
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108–10Fh
250
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200–207h
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208–20Fh
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FF0–FF3h
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2.19 PCU MCHBAR Registers
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5880–5883h
256
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5888–588Bh
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Report Register
258
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Temperature Report Register
259
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Graphics Engine (GT)
260
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5D10–5D17h
261
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2.20 PXPEPBAR Registers
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