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Datasheet 29

Electrical Specifications

2.8.3 Phase Lock Loop (PLL) and Filter

An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is

used for the PLL. Refer to Table 5 for DC specifications.

2.8.4 BCLK[1:0] Specifications (CK505 based Platforms)

Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L RESERVED

L L H RESERVED

L H H RESERVED

LH L200 MHz

H H L RESERVED

H H H RESERVED

H L H RESERVED

H L L RESERVED

Table 17. Front Side Bus Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Input Low Voltage -0.30 N/A N/A V 3

2. "Steady state" voltage, not including overshoot or undershoot.

Input High Voltage N/A N/A 1.15 V 3

CROSS(abs)

Absolute Crossing Point 0.300 N/A 0.550 V 3, 4

3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0

equals the falling edge of BCLK1.

4. V

Havg

is the statistical average of the V

measured by the oscilloscope.

5. The crossing point must meet the absolute and relative crossing point specifications

simultaneously.

ΔV

CROSS

Range of Crossing Points N/A N/A 0.140 V 3, 4

Overshoot N/A N/A 1.4 V 3

6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as

the absolute value of the minimum voltage.

Undershoot -0.300 N/A N/A V 3

SWING

Differential Output Swing 0.300 N/A N/A V 5

7. Measurement taken from differential waveform.

Input Leakage Current -5 N/A 5 μA

Cpad Pad Capacitance .95 1.2 1.45 pF

8. Cpad includes die capacitance only. No package parasitics are included.

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 101 102

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