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Document Number: 318924-001Intel® Celeron® Dual-Core Processor E1000Δ SeriesDatasheetJanuary 2008

Introduction10 Datasheet1.1.1 Processor TerminologyCommonly used terms are explained here for clarification:• Intel® Celeron® Dual-Core processor E100

Boxed Processor Specifications100 Datasheet

Datasheet 101Debug Tools Specifications8 Debug Tools Specifications8.1 Logic Analyzer Interface (LAI)Intel is working with two logic analyzer vendors

Debug Tools Specifications102 Datasheet

Datasheet 11Introduction1.2 ReferencesMaterial and concepts available in the following documents may be beneficial when reading this document.§ §Table

Introduction12 Datasheet

Datasheet 13Electrical Specifications2 Electrical SpecificationsThis chapter describes the electrical characteristics of the processor interfaces and

Electrical Specifications14 Datasheet2.2.3 FSB DecouplingThe processor integrates signal termination on the die. In addition, some of the high frequen

Datasheet 15Electrical SpecificationsTable 2. Voltage Identification DefinitionVID6 VID5 VID4 VID3 VID2 VID1 VCC_MAXVID6 VID5 VID4 VID3 VID2 VID1 VCC_

Electrical Specifications16 Datasheet2.4 Market Segment Identification (MSID)The MSID[1:0] signals may be used as outputs to determine the Market Segm

Datasheet 17Electrical SpecificationsThe TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resis

Electrical Specifications18 DatasheetNOTES:1. For functional operation, all processor electrical, signal quality, mechanical and thermal specification

Datasheet 19Electrical Specifications2.6.2 DC Voltage and Current SpecificationTable 5. Voltage and Current SpecificationsSymbol Parameter Min Typ Max

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO AN

Electrical Specifications20 DatasheetTable 6. VCC Static and Transient Tolerance for ProcessorsICC (A)Voltage Deviation from VID Setting (V)1, 2, 3, 4

Datasheet 21Electrical SpecificationsNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sho

Electrical Specifications22 DatasheetNOTES:1. VOS is measured overshoot voltage.2. TOS is measured time duration above VID.2.6.4 Die Voltage Validatio

Datasheet 23Electrical Specifications2.7.1 FSB Signal GroupsThe front side bus signals have been combined into groups by buffer type. GTL+ input signa

Electrical Specifications24 Datasheet3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration op

Datasheet 25Electrical Specifications2.7.3 Processor DC SpecificationsThe processor DC specifications in this section are defined at the processor cor

Electrical Specifications26 Datasheet.2.7.3.1 GTL+ Front Side Bus SpecificationsIn most cases, termination resistors are not required as these are int

Datasheet 27Electrical SpecificationsTable 14. GTL+ Bus Voltage DefinitionsSymbol Parameter Min Typ Max Units Notes1NOTES:1. Unless otherwise noted, a

Electrical Specifications28 Datasheet2.8 Clock Specifications2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor ClockingBCLK[1:0] directly controls

Datasheet 29Electrical Specifications2.8.3 Phase Lock Loop (PLL) and FilterAn on-die PLL filter solution will be implemented on the processor. The VCC

Datasheet 3Contents1Introduction...91.1 Ter

Electrical Specifications30 DatasheetFigure 3. Differential Clock WaveformFigure 4. Differential Clock Crosspoint SpecificationHigh TimePeriodVCROSSCL

Datasheet 31Electrical Specifications2.8.5 BCLK[1:0] Specifications (CK410 based Platforms)Table 18. Front Side Bus Differential BCLK SpecificationsSy

Electrical Specifications32 Datasheet2.9 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel

Datasheet 33Package Mechanical Specifications3 Package Mechanical SpecificationsThe processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) pac

Package Mechanical Specifications34 DatasheetFigure 8. Processor Package Drawing Sheet 1 of 3

Datasheet 35Package Mechanical SpecificationsFigure 9. Processor Package Drawing Sheet 2 of 3

Package Mechanical Specifications36 DatasheetFigure 10. Processor Package Drawing Sheet 3 of 3

Datasheet 37Package Mechanical Specifications3.2 Processor Component Keep-Out ZonesThe processor may contain components on the substrate that define c

Package Mechanical Specifications38 Datasheet3.5 Package Insertion SpecificationsThe processor can be inserted into and removed from a LGA775 socket 1

Datasheet 39Package Mechanical Specifications3.9 Processor Land CoordinatesFigure 12 shows the top view of the processor land coordinates. The coordin

4 Datasheet5.2.2 Thermal Monitor 2 ...775.2.3 On-Demand Mode...

Package Mechanical Specifications40 Datasheet

Datasheet 41Land Listing and Signal Descriptions4 Land Listing and Signal DescriptionsThis chapter provides the processor land assignment and signal d

Land Listing and Signal Descriptions42 DatasheetFigure 13. land-out Diagram (Top View – Left Side)30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15ANVCC

Datasheet 43Land Listing and Signal DescriptionsFigure 14. land-out Diagram (Top View – Right Side)14 13 12 11 10 9 8 7 6 5 4 3 2 1VCC VSS VCC VCC VSS

Land Listing and Signal Descriptions44 DatasheetTable 23. Alphabetical Land AssignmentsLand NameLand #Signal Buffer TypeDirectionA3# L5 Source Synch I

Land Listing and Signal DescriptionsDatasheet 45D22# D10 Source Synch Input/OutputD23# F11 Source Synch Input/OutputD24# F12 Source Synch Input/Output

Land Listing and Signal Descriptions46 DatasheetFC33 H16 Power/OtherFC34 J17 Power/OtherFC35 H4 Power/OtherFC36 AD3 Power/OtherFC37 AB3 Power/OtherFC3

Land Listing and Signal DescriptionsDatasheet 47TRDY# E3 Common Clock InputTRST# AG1 TAP InputVCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power

Land Listing and Signal Descriptions48 DatasheetVCC AJ18 Power/Other VCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power

Land Listing and Signal DescriptionsDatasheet 49VCC J28 Power/Other VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Other VCC J9 Power/Other

Datasheet 5Figures1VCC Static and Transient Tolerance for Processors...212VCC Overshoot Example

Land Listing and Signal Descriptions50 DatasheetVID0 AM2 Power/Other OutputVID1 AL5 Power/Other OutputVID2 AM3 Power/Other OutputVID3 AL6 Power/Other

Land Listing and Signal DescriptionsDatasheet 51VSS AG23 Power/Other VSS AG24 Power/Other VSS AG7 Power/Other VSS AH1 Power/Other VSS AH10 Power/O

Land Listing and Signal Descriptions52 DatasheetVSS B24 Power/Other VSS B5 Power/Other VSS B8 Power/Other VSS C10 Power/Other VSS C13 Power/Other

Land Listing and Signal DescriptionsDatasheet 53VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other

Land Listing and Signal Descriptions54 DatasheetTable 24. Numerical Land AssignmentLand #Land NameSignal Buffer TypeDirectionA2 VSS Power/Other A3 RS

Land Listing and Signal DescriptionsDatasheet 55C20 DBI3# Source Synch Input/OutputC21 D58# Source Synch Input/OutputC22 VSS Power/Other C23 VCCIOPLL

Land Listing and Signal Descriptions56 DatasheetF11 D23# Source Synch Input/OutputF12 D24# Source Synch Input/OutputF13 VSS Power/Other F14 D28# Sour

Land Listing and Signal DescriptionsDatasheet 57H30 BSEL1 Power/Other OutputJ1 VTT_OUT_LEFT Power/Other OutputJ2 FC3 Power/OtherJ3 FC22 Power/Other J

Land Listing and Signal Descriptions58 DatasheetM30 VCC Power/Other N1 PWRGOOD Power/Other InputN2 IGNNE# Asynch CMOS InputN3 VSS Power/Other N4 RES

Land Listing and Signal DescriptionsDatasheet 59U28 VCC Power/Other U29 VCC Power/OtherU30 VCC Power/Other V1 MSID1 Power/Other OutputV2 RESERVEDV3

6 DatasheetTables1 References ...112 Voltag

Land Listing and Signal Descriptions60 DatasheetAB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power

Land Listing and Signal DescriptionsDatasheet 61AF12 VCC Power/Other AF13 VSS Power/Other AF14 VCC Power/Other AF15 VCC Power/Other AF16 VSS Power

Land Listing and Signal Descriptions62 DatasheetAH30 VCC Power/Other AJ1 BPM1# Common Clock Input/OutputAJ2 BPM0# Common Clock Input/OutputAJ3 ITP_CL

Land Listing and Signal DescriptionsDatasheet 63AL18 VCC Power/Other AL19 VCC Power/Other AL20 VSS Power/Other AL21 VCC Power/Other AL22 VCC Power

Land Listing and Signal Descriptions64 Datasheet4.2 Alphabetical Signals ReferenceTable 25. Signal Description (Sheet 1 of 9)Name Type DescriptionA[3

Land Listing and Signal DescriptionsDatasheet 65BPM[5:0]#Input/OutputBPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. Th

Land Listing and Signal Descriptions66 DatasheetD[63:0]#Input/OutputD[63:0]# (Data) are the data signals. These signals provide a 64-bit data path bet

Land Listing and Signal DescriptionsDatasheet 67DEFER# InputDEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order c

Land Listing and Signal Descriptions68 DatasheetHIT#HITM#Input/OutputInput/OutputHIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop op

Land Listing and Signal DescriptionsDatasheet 69LOCK#Input/OutputLOCK# indicates to the system that a transaction must occur atomically. This signal m

Datasheet 7Intel® Celeron® Dual-Core Processor E1000Δ Series The Intel® Celeron® Dual-Core processor E1000 series deliver Intel's advanced, power

Land Listing and Signal Descriptions70 DatasheetRS[2:0]# InputRS[2:0]# (Response Status) are driven by the response agent (the agent responsible for c

Datasheet 71Land Listing and Signal DescriptionsTHERMTRIP# OutputIn the event of a catastrophic cooling failure, the processor will automatically shut

Land Listing and Signal Descriptions72 Datasheet§ §VRDSEL InputThis input should be left as a no connect in order for the processor to boot. The proce

Datasheet 73Thermal Specifications and Design Considerations5 Thermal Specifications and Design Considerations5.1 Processor Thermal SpecificationsThe

Thermal Specifications and Design Considerations74 DatasheetThe case temperature is defined at the geometric top center of the processor. Analysis ind

Datasheet 75Thermal Specifications and Design ConsiderationsTable 27. Thermal Profile Power (W)Maximum Tc (°C)PowerMaximum Tc (°C)PowerMaximum Tc (°C)

Thermal Specifications and Design Considerations76 Datasheet5.1.2 Thermal MetrologyThe maximum and minimum case temperatures (TC) for the processor is

Datasheet 77Thermal Specifications and Design Considerationsunder-designed thermal solution that is not able to prevent excessive activation of the TC

Thermal Specifications and Design Considerations78 DatasheetThe PROCHOT# signal is asserted when a high temperature situation is detected, regardless

Datasheet 79Thermal Specifications and Design Considerations5.2.4 PROCHOT# SignalAn external signal, PROCHOT# (processor hot), is asserted when the pr

8 DatasheetRevision History§ §Revision NumberDescription Date-001 • Initial release January 2008

Thermal Specifications and Design Considerations80 Datasheet5.3 Thermal DiodeThe processor incorporates an on-die PNP transistor where the base emitte

Datasheet 81Thermal Specifications and Design ConsiderationsNOTES:1. Intel does not support or recommend operation of the thermal diode under reverse

Thermal Specifications and Design Considerations82 Datasheet5.4 Platform Environment Control Interface (PECI)5.4.1 IntroductionPECI offers an interfac

Datasheet 83Thermal Specifications and Design Considerations..Figure 19. Conceptual Fan Control on PECI-Based PlatformsMinMaxFan Speed(RPM)TCONTROLSet

Thermal Specifications and Design Considerations84 Datasheet5.4.2 PECI Specifications5.4.2.1 PECI Device AddressThe PECI device address for the socket

Datasheet 85Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The processor samples the

Features86 Datasheet6.2 Clock Control and Low Power StatesThe processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption b

Datasheet 87Features6.2.2.1 HALT Powerdown StateHALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instruc

Features88 Datasheet6.2.3.1 Stop-Grant State When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after

Datasheet 89Features6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop StateThe processor will remain in the lower bus ratio and VID operati

Datasheet 9Introduction1 IntroductionThe Intel® Celeron® Dual-Core processor E1000 series combines the performance of the current generation of deskto

Features90 Datasheet

Datasheet 91Boxed Processor Specifications7 Boxed Processor SpecificationsThe processor will also be offered as an Intel boxed processor. Intel boxed

Boxed Processor Specifications92 Datasheet7.1 Mechanical Specifications7.1.1 Boxed Processor Cooling Solution DimensionsThis section documents the mec

Datasheet 93Boxed Processor SpecificationsNOTES:1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanica

Boxed Processor Specifications94 Datasheet7.1.2 Boxed Processor Fan Heatsink WeightThe boxed processor fan heatsink will not weigh more than 550 grams

Datasheet 95Boxed Processor SpecificationsFigure 26. Boxed Processor Fan Heatsink Power Cable Connector DescriptionTable 33. Fan Heatsink Power and Si

Boxed Processor Specifications96 Datasheet7.3 Thermal SpecificationsThis section describes the cooling requirements of the fan heatsink solution used

Datasheet 97Boxed Processor Specifications Figure 28. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)Figure 29. Boxed Process

Boxed Processor Specifications98 Datasheet7.3.2 Fan Speed Control OperationIf the boxed processor fan heatsink 4-pin connector is connected to a 3-pin

Datasheet 99Boxed Processor SpecificationsIf the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the mothe