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6.0 Signal Description

This chapter describes the processor signals. The signals are arranged in functional

groups according to the associated interface or category. The following notations are

used to describe the signal type.

Notation

Signal Type

I Input pin

O Output pin

I/O Bi-directional Input/Output pin

The signal description also includes the type of buffer used for the particular signal

(see the following table).

Table 24. Signal Description Buffer Types

Signal Description

CMOS CMOS buffers. 1.05V- tolerant

Diff Clk Differential clock

DDR3L/DDR3L-

DDR3L/DDR3L-RS buffers: 1.35 V-tolerant

Analog reference or output. May be used as a threshold voltage or for buffer

compensation

GTL Gunning Transceiver Logic signaling technology

Ref Voltage reference signal

Asynchronous

Signal has no timing relationship with any reference clock.

1. Qualifier for a buffer type.

System Memory Interface Signals

Table 25. DDR3L / DDR3L-RS Memory Down Channel A and B Memory Signals

Signal Name Description Direction /

Buffer Type

SA_CK[0]/SA_CK#[0]

SB_CK[0]/SB_CK#[0]

Clocks: CK and its complement CK# signal make up a

differential clock pair. The crossing of the positive edge of CK

and the negative edge of its complement CK# are used to

sample the command and control signals.

SA_MA[15:0],

SB_MA[15:0]

Memory Address: These signals are used to provide the

multiplexed row and column address.

SA_BS[2:0], SB_BS[2;0]

Bank Select: Signals used to define which bank a command

is being applied to.

SA_WE#, SB_WE#

Write Enable: These signals are used with RAS# and CAS#

to define the command being entered.

continued...

6.1

Processor—Signal Description

5th Generation Intel

Core

™

Processor Family, Intel

Core

™

M Processor Family, Mobile Intel

Pentium

Processor Family, and

Mobile Intel

Celeron

Processor Family

Datasheet – Volume 1 of 2 March 2015

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