Intel AV8062700837205 Arkusz Danych Strona 28
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Oceniono. / 5. Na podstawie oceny klientów
Figure 5. HDMI* Overview
HDMI Source
HDMI Sink
TMDS Data Channel 0
Hot-Plug Detect
HDMI Tx HDMI Rx
TMDS
Data
Channel
1
TMDS Data Channel 2
TMDS Clock Channel
CEC Line (optional)
Display Data Channel (DDC)
embedded DisplayPort*
The embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort
standard oriented towards applications such as notebook and All-In-One PCs. Like
DisplayPort, embedded DisplayPort also consists of a Main Link, Auxiliary channel, and
an optional Hot-Plug Detect signal.
Integrated Audio
• HDMI and display port interfaces carry audio along with video.
• Processor supports two DMA controllers to output two High Definition audio
streams on two digital ports simultaneously.
• Supports only the internal HDMI and DP CODECs.
Table 8. Processor Supported Audio Formats over HDMI*and DisplayPort*
Audio Formats HDMI* DisplayPort*
AC-3 Dolby* Digital Yes Yes
Dolby Digital Plus Yes Yes
DTS-HD* Yes Yes
LPCM, 192 kHz/24 bit, 8 Channel Yes Yes
Dolby TrueHD, DTS-HD Master Audio*
(Lossless Blu-Ray Disc* Audio Format)
Yes Yes
Processor—Interfaces
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2 March 2015
28 Order No.: 330834-004v1
- Datasheet – Volume 1 of 2 1
- Contents 3
- Revision History 9
- 1.0 Introduction 10
- Supported Technologies 11
- Power Management Support 12
- Thermal Management Support 12
- Related Documents 16
- 2.0 Interfaces 18
- System Memory Timing Support 19
- Fast Memory Access (Intel 20
- System Memory Frequency 21
- Processor Graphics 22
- Source Device Sink Device 27
- HDMI Source 28
- HDMI Sink 28
- PECI Bus Architecture 31
- <10pF/Node 32
- 3.0 Technologies 33
- Technology) 38
- 64 Architecture x2APIC 40
- G0 – Working 44
- G1 – Sleeping 44
- G3 – Mechanical Off 44
- G2 – Soft Off 44
- Table 13. System States 45
- Enhanced Intel 46
- SpeedStep 46
- Technology Key Features 46
- Thread 0 Thread 1 47
- Core 0 State 47
- Core N State 47
- Processor Package State 47
- Core C-State Rules 48
- Package C-States 50
- Package C0 51
- Initialization Role of CKE 56
- Conditional Self-Refresh 56
- 4.3.2.1 56
- 4.3.2.2 56
- Dynamic Power-Down 57
- DRAM I/O Power Management 57
- 4.3.2.3 57
- 4.3.2.4 57
- Graphics Power Management 58
- 5.0 Thermal Management 60
- Package Power Control 61
- Turbo Time Parameter 62
- Configurable TDP 63
- Low-Power Mode 63
- Thermal Management Features 66
- Digital Thermal Sensor 68
- PROCHOT# Signal 69
- On-Demand Mode 70
- MSR Based On-Demand Mode 71
- 5.6.4.1 71
- 5.6.4.2 71
- 6.0 Signal Description 72
- Table 31. Testability Signals 75
- Power Sequencing Signals 77
- Processor Power Signals 77
- Sense Signals 78
- Reserved or Unused Signals 85
- Signal Groups 85
- Table 42. Vcc Sustain (Vcc 89
- Characteristics 94
- Input Device Hysteresis 95
- 8.0 Package Specifications 96
- (BGA1234) 98
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