Intel CONTROLLERS 413808 Instrukcja Użytkownika Pobierz pdf (Strona 683)

31:5 000 0000h Reserved

40

2

Clear to Send (CTS): This bit is the complement of the Clear to Send (CTS#) input.

This bit is equivalent to bit RTS of the Modem Control register when LOOP in the

MCR is set to 1.

0 = CTS# pin is 1

1 = CTS# pin is 0

3:1 000

2

Reserved

00

2

Delta Clear To Send (DCTS):

0 = No change in CTS# pin since last read of MSR

1 = CTS# pin has changed state

1 2 ... 678 679 680 681 682 683 684 685 686 687 688 ... 823 824

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