Intel E3-1275 Arkusz Danych Pobierz pdf (Strona 209)

Datasheet, Volume 2 209

Processor Configuration Registers

2.13.4 TC_SRFTP_C0—Self-Refresh Timing Parameters Register

This register provides Self-refresh timing parameters.

2.13.5 PM_PDWN_config_C0—Power-down Configuration

This register defines the power-down (CKE-off) operation – power-down mode, idle

timer, and global / per rank decision.

B/D/F/Type 0/0/0/MCHBAR MC0

Address Offset: 42A4–42A7h

Reset Value: 0000_B000h

Access: RW-L

Size: 32 bits

Bit Attr

Reset

Value

RST/

PWR

Description

31:16 RO 0h Reserved

15:12 RW-L Bh

Delay From SR Exit to First DDR Command

tXS = tRFC+10ns. Setup of tXS_offset is # of cycles for 10 ns.

Range is between 3 and 11 DCLK cycles

11:0 RO 0h Reserved

B/D/F/Type: 0/0/0/MCHBAR MC0

Address Offset: 40B0-40B3h

Reset Value: 0000_0000h

Access: RW-L

Size: 32 bits

BIOS Optimal Default: 00000h

Bit Attr

Reset

Value

RST/

PWR

Description

31:13 RO 0h Reserved

12 RW-L 0b Uncore

Global power-down (GLPDN)

1 = Power-down decision is global for channel.

0 = A separate decision is taken for each rank.

11:0 RO 0h Reserved

1 2 ... 204 205 206 207 208 209 210 211 212 213 214 ... 299 300

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Intel E3-1275 Arkusz Danych Strona 209