Intel AT80571PH0673M Arkusz Danych Pobierz pdf (Strona 34)

Electrical Specifications

34 Datasheet

5. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is

measured using a ±75 mV window centered on the average cross point where Clock rising

meets Clock# falling. The median cross point is used to calculate the voltage thresholds

the oscilloscope is to use for the edge rate calculations.

6. Duty Cycle (High time/Period) must be between 40 and 60%

§ §

Figure 4. Differential Clock Waveform

Threshold

Region

Overshoot

Undershoot

Ringback

Margin

Rising Edge

Ringback

Falling Edge

Ringback

BCLK0

BCLK1

Tph

Tpl

Tp = T1: BCLK[1:0] period

T2: BCLK[1:0] period stability (not shown)

Tph = T3: BCLK[1:0] pulse high time

Tpl = T4: BCLK[1:0] pulse low time

T5: BCLK[1:0] rise time through the threshold region

T6: BCLK[1:0] fall time through the threshold region

CROSS (ABS

)

Figure 5. Measurement Points for Differential Clock Waveforms

+150 mV

-150 mV

0.0 V 0.0V

Slew_rise

+150mV

-150mV

V_swing

Slew _fall

Diff

T5 = BCLK[1:0] rise and fall time through the swing region

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 101 102

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Intel AT80571PH0673M Arkusz Danych Strona 34