Intel LF80537NF0411M Arkusz Danych Pobierz pdf (Strona 39)

Specification Update 39

The following figure will be modified to reflect this change:

Figure 12. System Bus Reset and Configuration Timings

BCLK

Reset

Configuration

A[31:3], SMI#,

INIT#

Valid

Tv = T13 (RESET# Pulse Width)

Tw = T45 (Reset Configuration Signals Setup Time)

Tx = T46 (Reset Configuration Signals A[31:3], SMI#, and INIT# Hold Time)

Ty = T47 (Reset Configuration signal BR0# Hold Time)

Valid

Configuration

BR0#

1 2 ... 34 35 36 37 38 39 40

Brak uwag

Intel LF80537NF0411M Arkusz Danych Strona 39