Intel LE80537VE001512 Arkusz Danych Pobierz pdf (Strona 44)

Errata

44 Specification Update

AR62. CPL-Qualified BTS May Report Incorrect Branch-From Instruction

Address

Problem: CPL (Current Privilege Level)-qualified BTS (Branch Trace Store) may report incorrect

branch-from instruction address under the following conditions:

• Either BTS_OFF_OS [9] or BTS_OFF_USR [10] is selected in IA32_DEBUGCTLC

MSR (1D9H).

• Privilege-level transitions occur between CPL > 0 and CPL 0 or vice versa.

Implication: Due to this erratum, the From address reported by BTS may be incorrect for the

described conditions.

Workaround: None identified

Status: For the steppings affected, see the Summary Tables of Changes.

AR63. PEBS Does Not Always Differentiate between CPL-Qualified Events

Problem: Performance monitoring counter configured to sample PEBS (Precise Event Based

Sampling) events at a certain privilege level may count samples at the wrong privilege

level.

Implication: Performance monitoring counter may be higher than expected for CPL-qualified

events. Do not use performance monitoring counters for precise event sampling when

the precise event is dependent on the CPL value.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

AR64. PMI May Be Delayed to Next PEBS Event

Problem: After a PEBS (Precise Event-Based Sampling) event, the PEBS index is compared with

the PEBS threshold, and the index is incremented with every event. If PEBS index is

equal to the PEBS threshold, a PMI (Performance Monitoring Interrupt) should be

issued. Due to this erratum, the PMI may be delayed by one PEBS event.

Implication: Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one

PEBS event.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

1 2 ... 39 40 41 42 43 44 45 46 47 48 49 ... 62 63

Brak uwag

Intel LE80537VE001512 Arkusz Danych Strona 44