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Document Number: 316852-001Intel® Core™2 Extreme Quad-Core Processor QX6800ΔDatasheet— on 65 nm Process in the 775-land LGA Package supporting Intel®

Introduction10 Datasheet1.1.1 Processor Packaging TerminologyCommonly used terms are explained here for clarification:• Intel® Core™2 Extreme quad-cor

Datasheet 11Introductionthis virtualization hardware provides a new architecture upon which the operating system can run directly, it removes the need

Introduction12 Datasheet

Datasheet 13Electrical Specifications2 Electrical SpecificationsThis chapter describes the electrical characteristics of the processor interfaces and

Electrical Specifications14 Datasheet2.3 Voltage IdentificationThe Voltage Identification (VID) specification for the processor is defined by the Volt

Datasheet 15Electrical SpecificationsTable 2. Voltage Identification DefinitionVID6 VID5 VID4 VID3 VID2 VID1 VCC_MAXVID6 VID5 VID4 VID3 VID2 VID1 VCC_

Electrical Specifications16 Datasheet2.4 Reserved, Unused, and TESTHI SignalsAll RESERVED lands must remain unconnected. Connection of these lands to

Datasheet 17Electrical Specifications2.5 Voltage and Current Specification2.5.1 Absolute Maximum and Minimum RatingsTable 3 specifies absolute maximum

Electrical Specifications18 Datasheet2.5.2 DC Voltage and Current SpecificationTable 4. Voltage and Current SpecificationsSymbol Parameter Min Typ Max

Datasheet 19Electrical SpecificationsTable 5. VCC Static and Transient ToleranceICC (A)Voltage Deviation from VID Setting (V)1, 2, 3, 4NOTES:1. The lo

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO AN

Electrical Specifications20 DatasheetNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sho

Datasheet 21Electrical SpecificationsNOTES:1. VOS is measured overshoot voltage.2. TOS is measured time duration above VID.2.5.4 Die Voltage Validatio

Electrical Specifications22 Datasheet2.6.1 FSB Signal GroupsThe front side bus signals have been combined into groups by buffer type. GTL+ input signa

Datasheet 23Electrical SpecificationsNOTES:1. Refer to Section 4.2 for signal descriptions.2. In processor systems where no debug port is implemented

Electrical Specifications24 DatasheetTable 10. GTL+ Signal Group DC SpecificationsSymbol Parameter Min Max Unit Notes1NOTES:1. Unless otherwise noted,

Datasheet 25Electrical Specifications2.6.3.1 GTL+ Front Side Bus SpecificationsIn most cases, termination resistors are not required as these are inte

Electrical Specifications26 Datasheet2.7 Clock Specifications2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor ClockingBCLK[1:0] directly controls

Datasheet 27Electrical SpecificationsNOTES:1. Individual processors operate only at or below the rated frequency.2. Listed frequencies are not necessa

Electrical Specifications28 Datasheet2.7.4 BCLK[1:0] SpecificationsTable 16. Front Side Bus Differential BCLK SpecificationsSymbol Parameter Min Typ M

Datasheet 29Electrical Specifications2.8 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel

Datasheet 3Contents1Introduction...91.1 Ter

Electrical Specifications30 Datasheet

Datasheet 31Package Mechanical Specifications3 Package Mechanical SpecificationsThe processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) pac

Package Mechanical Specifications32 DatasheetFigure 6. Processor Package Drawing Sheet 1 of 3

Datasheet 33Package Mechanical SpecificationsFigure 7. Processor Package Drawing Sheet 2 of 3

Package Mechanical Specifications34 DatasheetFigure 8. Processor Package Drawing Sheet 3 of 3

Datasheet 35Package Mechanical Specifications3.2 Processor Component Keep-Out ZonesThe processor may contain components on the substrate that define c

Package Mechanical Specifications36 Datasheet3.5 Package Insertion SpecificationsThe processor can be inserted into and removed from a LGA775 socket 1

Datasheet 37Package Mechanical Specifications3.9 Processor Land CoordinatesFigure 10 shows the top view of the processor land coordinates. The coordin

Package Mechanical Specifications38 Datasheet

Datasheet 39Land Listing and Signal Descriptions4 Land Listing and Signal DescriptionsThis chapter provides the processor land assignment and signal d

4 Datasheet5.2.5 THERMTRIP# Signal...785.3 Platform Environment Control I

Land Listing and Signal Descriptions40 DatasheetFigure 11. land-out Diagram (Top View – Left Side)30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15ANVCC

Datasheet 41Land Listing and Signal DescriptionsFigure 12. land-out Diagram (Top View – Right Side)14 13 12 11 10 9 8 7 6 5 4 3 2 1VCC VSS VCC VCC VSS

Land Listing and Signal Descriptions42 DatasheetTable 21. Alphabetical Land AssignmentsLand NameLand #Signal Buffer TypeDirectionA3# L5 Source Synch I

Land Listing and Signal DescriptionsDatasheet 43D24# F12 Source Synch Input/OutputD25# D13 Source Synch Input/OutputD26# E13 Source Synch Input/Output

Land Listing and Signal Descriptions44 DatasheetGTLREF1 H2 Power/Other InputGTLREF2 G10 Power/Other Input GTLREF3 F2 Power/Other InputHIT# D4 Common C

Land Listing and Signal DescriptionsDatasheet 45VCC AD28 Power/Other VCC AD29 Power/Other VCC AD30 Power/Other VCC AD8 Power/Other VCC AE11 Power/

Land Listing and Signal Descriptions46 DatasheetVCC AL18 Power/Other VCC AL19 Power/Other VCC AL21 Power/Other VCC AL22 Power/Other VCC AL25 Power

Land Listing and Signal DescriptionsDatasheet 47VCC N29 Power/Other VCC N30 Power/Other VCC N8 Power/Other VCC P8 Power/Other VCC R8 Power/Other

Land Listing and Signal Descriptions48 DatasheetVSS AB30 Power/Other VSS AB7 Power/Other VSS AC3 Power/Other VSS AC6 Power/Other VSS AC7 Power/Oth

Land Listing and Signal DescriptionsDatasheet 49VSS AL10 Power/Other VSS AL13 Power/Other VSS AL16 Power/Other VSS AL17 Power/Other VSS AL20 Power

Datasheet 5Figures1VCC Static and Transient Tolerance...202VCC Overshoot Exa

Land Listing and Signal Descriptions50 DatasheetVSS H22 Power/Other VSS H23 Power/Other VSS H24 Power/Other VSS H25 Power/Other VSS H26 Power/Othe

Land Listing and Signal DescriptionsDatasheet 51VTT B26 Power/Other VTT B27 Power/Other VTT B28 Power/Other VTT B29 Power/Other VTT B30 Power/Othe

Land Listing and Signal Descriptions52 DatasheetTable 22. Numerical Land AssignmentLand #Land NameSignal Buffer TypeDirectionA2 VSS Power/Other A3 RS

Land Listing and Signal DescriptionsDatasheet 53C26 VTT Power/Other C27 VTT Power/Other C28 VTT Power/Other C29 VTT Power/Other C30 VTT Power/Othe

Land Listing and Signal Descriptions54 DatasheetF23 RESERVED F24 TESTHI7 Power/Other InputF25 TESTHI2 Power/Other InputF26 TESTHI0 Power/Other Input

Land Listing and Signal DescriptionsDatasheet 55J18 VCC Power/Other J19 VCC Power/Other J20 VCC Power/Other J21 VCC Power/Other J22 VCC Power/Othe

Land Listing and Signal Descriptions56 DatasheetP8 VCC Power/Other P23 VSS Power/Other P24 VSS Power/Other P25 VSS Power/Other P26 VSS Power/Other

Land Listing and Signal DescriptionsDatasheet 57W26 VCC Power/Other W27 VCC Power/Other W28 VCC Power/Other W29 VCC Power/Other W30 VCC Power/Othe

Land Listing and Signal Descriptions58 DatasheetAD30 VCC Power/Other AE1 TCK TAP InputAE2 VSS Power/Other AE3 FC18 Power/Other AE4 RESERVED AE5 V

Land Listing and Signal DescriptionsDatasheet 59AG24 VSS Power/Other AG25 VCC Power/Other AG26 VCC Power/Other AG27 VCC Power/Other AG28 VCC Power

6 DatasheetIntel® Core™2 Extreme Quad-Core Processor QX6800 Features The Intel Core™2 Extreme quad-core processor QX6800 delivers Intel's advance

Land Listing and Signal Descriptions60 DatasheetAK18 VCC Power/Other AK19 VCC Power/Other AK20 VSS Power/Other AK21 VCC Power/Other AK22 VCC Power

Land Listing and Signal DescriptionsDatasheet 61AN11 VCC Power/Other AN12 VCC Power/Other AN13 VSS Power/Other AN14 VCC Power/Other AN15 VCC Power

Land Listing and Signal Descriptions62 Datasheet4.2 Alphabetical Signals ReferenceTable 23. Signal Description (Sheet 1 of 9)Name Type DescriptionA[3

Datasheet 63Land Listing and Signal DescriptionsBPM[5:0]#BPMb[3:0]#Input/OutputBPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and perfor

Land Listing and Signal Descriptions64 DatasheetD[63:0]#Input/OutputD[63:0]# (Data) are the data signals. These signals provide a 64-bit data path bet

Datasheet 65Land Listing and Signal DescriptionsDEFER# InputDEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-orde

Land Listing and Signal Descriptions66 DatasheetHIT#HITM#Input/OutputInput/OutputHIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop op

Datasheet 67Land Listing and Signal DescriptionsLOCK#Input/OutputLOCK# indicates to the system that a transaction must occur atomically. This signal m

Land Listing and Signal Descriptions68 DatasheetRS[2:0]# InputRS[2:0]# (Response Status) are driven by the response agent (the agent responsible for c

Datasheet 69Land Listing and Signal DescriptionsTHERMTRIP# OutputIn the event of a catastrophic cooling failure, the processor will automatically shut

Datasheet 7Revision History§ §Revision NumberDescription Date-001 • Initial release April 2007

Land Listing and Signal Descriptions70 Datasheet§ §VID_SELECT OutputThis land is tied high on the processor package and is used by the VR to choose th

Datasheet 71Thermal Specifications and Design Considerations5 Thermal Specifications and Design Considerations5.1 Processor Thermal SpecificationsThe

Thermal Specifications and Design Considerations72 Datasheetcomplete thermal solution designs target the Thermal Design Power (TDP) indicated in Table

Datasheet 73Thermal Specifications and Design ConsiderationsTable 25. Thermal Profile 130 W ProcessorsPower (W)Maximum Tc (°C)Power (W)Maximum Tc (°C)

Thermal Specifications and Design Considerations74 DatasheetFigure 13. Thermal Profile 130 W Processors35.040.045.050.055.060.00 102030405060708090100

Datasheet 75Thermal Specifications and Design Considerations5.1.2 Thermal MetrologyThe maximum and minimum case temperatures (TC) for the processor is

Thermal Specifications and Design Considerations76 Datasheetunder-designed thermal solution that is not able to prevent excessive activation of the TC

Datasheet 77Thermal Specifications and Design ConsiderationsThe PROCHOT# signal is asserted when a high temperature situation is detected, regardless

Thermal Specifications and Design Considerations78 Datasheetthe system tries to enable On-Demand mode at the same time the TCC is engaged, the factory

Datasheet 79Thermal Specifications and Design Considerations5.3 Platform Environment Control Interface (PECI)5.3.1 IntroductionPECI offers an interfac

8 Datasheet

Thermal Specifications and Design Considerations80 Datasheet5.3.2 PECI Specifications5.3.2.1 PECI Device AddressThe PECI register resides at address 3

Datasheet 81Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The processor samples the

Features82 Datasheet6.2.1 Normal StateThis is the normal operating state for the processor.6.2.2 HALT and Extended HALT Powerdown StatesThe processor

Datasheet 83FeaturesThe system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# inter

Features84 Datasheet6.2.4 Extended HALT Snoop or HALT Snoop State,Stop Grant Snoop StateThe Extended HALT Snoop State is used in conjunction with the

Datasheet 85Boxed Processor Specifications7 Boxed Processor SpecificationsThe processor will also be offered as an Intel boxed processor. Intel boxed

Boxed Processor Specifications86 Datasheet

Datasheet 87Debug Tools Specifications8 Debug Tools Specifications8.1 Logic Analyzer Interface (LAI)Intel is working with two logic analyzer vendors t

Debug Tools Specifications88 Datasheet

Datasheet 9Introduction1 IntroductionThe Intel® Core™2 Extreme quad-core processor QX6800 is a desktop quad core processor that combines the performan